AU2021102694A4 - System and method for ip’s for ethernet and hdmi using xilinx vivado for iot applications - Google Patents
System and method for ip’s for ethernet and hdmi using xilinx vivado for iot applications Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/436—Interfacing a local distribution network, e.g. communicating with another STB or one or more peripheral devices inside the home
- H04N21/4363—Adapting the video stream to a specific local network, e.g. a Bluetooth® network
- H04N21/43632—Adapting the video stream to a specific local network, e.g. a Bluetooth® network involving a wired protocol, e.g. IEEE 1394
- H04N21/43635—HDMI
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- G—PHYSICS
- G16—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR SPECIFIC APPLICATION FIELDS
- G16Y—INFORMATION AND COMMUNICATION TECHNOLOGY SPECIALLY ADAPTED FOR THE INTERNET OF THINGS [IoT]
- G16Y10/00—Economic sectors
- G16Y10/75—Information technology; Communication
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- G—PHYSICS
- G16—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR SPECIFIC APPLICATION FIELDS
- G16Y—INFORMATION AND COMMUNICATION TECHNOLOGY SPECIALLY ADAPTED FOR THE INTERNET OF THINGS [IoT]
- G16Y30/00—IoT infrastructure
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/2803—Home automation networks
- H04L12/2805—Home Audio Video Interoperability [HAVI] networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/2854—Wide area networks, e.g. public data networks
- H04L12/2856—Access arrangements, e.g. Internet access
- H04L12/2869—Operational details of access network equipments
- H04L12/2878—Access multiplexer, e.g. DSLAM
- H04L12/2879—Access multiplexer, e.g. DSLAM characterised by the network type on the uplink side, i.e. towards the service provider network
- H04L12/2881—IP/Ethernet DSLAM
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/2803—Home automation networks
- H04L2012/2847—Home automation networks characterised by the type of home appliance used
- H04L2012/2849—Audio/video appliances
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
- H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
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Abstract
The present disclosure relates to a system and a method for IP's for ethernet and
HDMI using Xilinx Viva do for internet of things application. The system comprises: an
ethernet module to handle communication to send and receive data between devices via an
ethernet controller; a HDMI module to transfer video and audio data between two devices via
a HDMI buffer; and a memory module to handle communication with said ethernet and
HDMI and a DDR2 SRAM (Double Data Rate Synchronous Dynamic Random-Access
Memory) memory on a board. The method comprises the following steps: handling
communication using an ethernet module to send and receive data between devices via an
ethernet controller; transferring video and audio data between two devices using a HDMI
module via a HDMI buffer; and handling communication with said ethernet and HDMI and a
DDR2 SRAM (Double Data Rate Synchronous Dynamic Random-Access Memory) memory
on a board through a memory module.
17
100
ETHERNET HDMI MEMORY
MODULE MODULE MODULE
102 104 106
Figure 1
200
Handling communication using an ethernet module to send and receive IV 202
data between devicesvia an ethernet controller 1 W
Transferringvideoand audio data between twodevicesusingaHDMI
module via aHDMl buffer. [i 20
Handling communication with said ethemetand HDMI and a DDR2 SRAM
(Double Data Rate Synchronous Dynamic Random-Access Memory)
memory on a board through a me mory module.
Figure 2
Description
ETHERNET HDMI MEMORY MODULE MODULE MODULE 102 104 106
Figure 1
200
Handling communication using an ethernet module to send and receive IV 202 data between devicesvia an ethernet controller 1 W
Transferringvideoandaudio data between twodevicesusingaHDMI module via aHDMl buffer. [i 20
Handling communication with said ethemetand HDMI and a DDR2 SRAM (Double Data Rate SynchronousDynamic Random-Access Memory) memory on a board through ame mory module.
Figure 2
The present disclosure relates to a system and a method for IP's for ethernet and HDMI using Xilinx Viva do for internet of things application.
Today, consumer electronic is used by almost everyone. The demand of electronic products increases every day, like TV' sand DVD-players, the cables that carries the video and audio data also needs to get develop. To transport data between two units without any distortion is important. The signals can be divided into two types, there is analog and digital form, and therefore the cables are arranged in the form of analog and digital signal. In this paper the focus will be on HDMI. One of them is that the length of the cable cannot be that long. The maximum length of a HDMI cable is 15 m, but it is rare to find any cables longer than 7.5 m in a store. To be able to extend the length between a HDMI source and a HDMI sink the medium the video data are sent on must be changed. The medium that is used for transmission of data is Ethernet cables. The maximum length for Ethernet cables is 100 m long.
The invention (US10673645B2) relates to a service management system communicates via wide area network with gateway devices located at respective user premises. The service management system remotely manages delivery of application services, which can be voice controlled, by a gateway, e.g., by selectively activating/deactivating service logic modules in the gateway. The service management system also may selectively provide secure communications and exchange of information among gateway devices and among associated endpoint devices. An exemplary service management system includes a router connected to the network and one or more computer platforms, for implementing management functions. Examples of the functions include a connection manager for controlling system communications with the gateway devices, an authentication manager for authenticating each gateway device and controlling the connection manager and a subscription manager for managing applications services and/or features offered by the gateway devices. A service manager, controlled by the subscription manager, distributes service specific configuration data to authenticated gateway devices.
The invention (US7992177B2) relates to a high-definition video transmitter and receiver are disclosed. The transmitter provides high-definition video to a one-point receiver or to multipoint receivers. The transmission network is asynchronous and the receiver re synchronizes the video. The transmission can be wired or wireless.
The invention (US8848608B1) relates to a method in one embodiment includes detecting a trigger on an electronic device and identifying an interface usage policy for an agent and a corresponding application on the electronic device. The method also includes selecting a first wireless interface of a plurality of wireless interfaces on the electronic device for a network session between an application process of the application and a remote node, with the first wireless interface being selected based on one or more criteria in the interface usage policy. In specific embodiments the electronic device is an on-board unit of a vehicle. In more specific embodiments a second wireless interface is selected based on the interface usage policy, the first and second wireless interfaces are different physical interfaces on the electronic device. In other specific embodiments, the first and second wireless interfaces are virtual interfaces of a single physical interface on the electronic device.
The invention (CN101448123B) relates to a transmitting device includes a video signal output unit, an image displaying unit, an information receiving unit, and a controller. The video-signal output unit outputs a video signal. The image displaying unit displays an image based on the video signal outputted from the video-signal output unit, on a first image display element. The signal transmitting unit transmits the video signal outputted from the video-signal output unit, to an external apparatus via a transmission path. The information receiving unit receives operational information transmitted from the external apparatus, on a display screen of a second image display of the external apparatus. The controller controls at least an operation of the video-signal output unit on the basis of the operational information received by the information receiving unit.
In order to overcome the above-mentioned drawbacks,there is a need to develop a system and a method for IP's for ethernet and HDMI using Xilinx Viva do for internet of things application.
The present disclosure relates to The present disclosure relates to a system and a method for IP's for ethernet and HDMI using Xilinx Viva do for internet of things application. For Wireless Communication, MIMO two port diversity slot antenna in terahertz range which is dependent on the coplanar waveguide (CPW) has been proposed. The monopole of right and left symmetric radiation is represented on the basis of the principle of coupling. The impact of varying the angle between transmission line and radiation dipole and the coplanar waveguide's shape on the antenna has been studied with the wide range of frequency band in which the antenna will be working.
In an embodiment, a system 100 for IP's for ethernet and HDMI using Xilinx Viva do for internet of things application comprises: an ethernet module 102 to handle communication to send and receive data between devices via an ethernet controller ;a HDMI module 104 to transfer video and audio data between two devices via a HDMI buffer; and a memory module 106 to handle communication with said ethernet and HDMI and a DDR2 SRAM (Double Data Rate Synchronous Dynamic Random-Access Memory) memory on a board.
In an embodiment, a method 200 for IP's for ethernet and HDMI using Xilinx Viva do for internet of things application comprises the following steps: at step 202,handling communication using an ethernet module to send and receive data between devices via an ethernet controller; at step 204,transferring video and audio data between two devices using a HDMI module via a HDMI buffer; and at step 206,handling communication with said ethernet and HDMI and a DDR2 SRAM (Double Data Rate Synchronous Dynamic Random Access Memory) memory on a board through a memory module.
To further clarify advantages and features of the present disclosure, a more particular description of the invention will be rendered by reference to specific embodiments thereof, which is illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. The invention will be described and explained with additional specificity and detail with the accompanying drawings.
These and other features, aspects, and advantages of the present disclosure will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein:
Figure 1 illustrates a system for IP's for ethernet and HDMI using Xilinx Viva do for internet of things application in accordance with an embodiment of the present disclosure.
Figure 2 illustrates a method for IP's for ethernet and HDMI using Xilinx Viva do for internet of things application in accordance with an embodiment of the present disclosure.
Figure 3 illustrates (a) Connection between Ethernet and HDMI; (b)Block diagram between Ethernet and HDMI; (c)Communication observed between transmitted and observed signal; and (d)Ethernet Frame in accordance with an embodiment of the present disclosure.
Figure 4 illustrates (a)Block Diagram over HDMI; (b)Time Diagram for data transmission over TMDS; and (c)Zynxc7zO2O-1CLG484in accordance with an embodiment of the present disclosure.
Figure 5 illustrates (a)Flow chart of Ethernet; (b)Flow chart of HDMI; and (c)Finite State Machine in accordance with an embodiment of the present disclosure.
Figure 6 illustrates (a) AXI Ethernet Subsystem; and (b)AXI HDMIin accordance with an embodiment of the present disclosure.
Further, skilled artisans will appreciate that elements in the drawings are illustrated for simplicity and may not have been necessarily been drawn to scale. For example, the flow charts illustrate the method in terms of the most prominent steps involved to help to improve understanding of aspects of the present disclosure. Furthermore, in terms of the construction of the device, one or more components of the device may have been represented in the drawings by conventional symbols, and the drawings may show only those specific details that are pertinent to understanding the embodiments of the present disclosure so as not to obscure the drawings with details that will be readily apparent to those of ordinary skill in the art having benefit of the description herein.
For the purpose of promoting an understanding of the principles of the invention, reference will now be made to the embodiment illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the invention is thereby intended, such alterations and further modifications in the illustrated system, and such further applications of the principles of the invention as illustrated therein being contemplated as would normally occur to one skilled in the art to which the invention relates.
It will be understood by those skilled in the art that the foregoing general description and the following detailed description are exemplary and explanatory of the invention and are not intended to be restrictive thereof.
Reference throughout this specification to "an aspect", "another aspect" or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrase "in an embodiment", "in another embodiment" and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.
The terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process or method that comprises a list of steps does not include only those steps but may include other steps not expressly listed or inherent to such process or method. Similarly, one or more devices or sub-systems or elements or structures or components proceeded by "comprises...a" does not, without more constraints, preclude the existence of other devices or other sub-systems or other elements or other structures or other components or additional devices or additional sub-systems or additional elements or additional structures or additional components. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The system, methods, and examples provided herein are illustrative only and not intended to be limiting.
Embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings.
Referring to Figure 1 illustrates a system for IP's for ethernet and HDMI using Xilinx Vivado for internet of things application in accordance with an embodiment of the present disclosure. A system 100 for IP's for ethernet and HDMI using Xilinx Viva do for internet of things application comprises: an ethernet module 102 to handle communication to send and receive data between devices via an ethernet controller; a HDMI module 104 to transfer video and audio data between two devices via a HDMI buffer; and a memory module 106 to handle communication with said ethernet and HDMI and a DDR2 SRAM (Double Data Rate Synchronous Dynamic Random-Access Memory) memory on a board.
Figure 2 illustrates a method for IP's for ethernet and HDMI using Xilinx Viva do for internet of things application in accordance with an embodiment of the present disclosure. A method 200 for IP's for ethernet and HDMI using Xilinx Viva do for internet of things application comprises the following steps: at step 202,handling communication using an ethernet module to send and receive data between devices via an ethernet controller; at step 204, transferring video and audio data between two devices using a HDMI module via a HDMI buffer; and at step 206, handling communication with said ethernet and HDMI and a DDR2 SRAM (Double Data Rate Synchronous Dynamic Random-Access Memory) memory on a board through a memory module.
Figure 3 illustrates (a) Connection between Ethernet and HDMI; (b) Block diagram between Ethernet and HDMI; (c) Communication observed between transmitted and observed signal; and (d) Ethernet Frame in accordance with an embodiment of the present disclosure.
The main task in the project is to design a device which can receive Ethernet frames and convert them into a HDMI signal that is sent out from the device. The device is based on a FPGA board. The system is fed with Ethernet frames through an Ethernet cable. On the output side the system generates a HDMI signal through a HDMI cable as shown in figure 3a.
There are three parts in this system (Ethernet, HDMI and Memory). Each of them will handle its own task. The Ethernet module will handle communication to the world via an Ethernet controller but also communication with the memory. The HDMI module will handle communication with the outside world via a HDMI buffer and to the memory. Finally, the memory module will handle communication with both Ethernet and HDMI and the DDR2 SRAM (Double Data Rate Synchronous Dynamic Random-Access Memory) memory on the board as shown in figure 3b.
Ethernet
Ethernet is used to send and receive data between devices. It is the most widely used in LAN (local area networking) technology in the world today. The official Ethernet standard today is the IEEE (Institute of Electrical and Electronics Engineers) 802.3 which is controlled by the IEEE. The Ethernet uses Carrier Sense Multiple Access with Collision Detection i.e., CSMA-CD protocol while transmitting with data. The sender while transmitting listens the medium collision.
Sender stops transmission if collision has occurred, which reduces channel wastage. A node monitors the media while transmitting. If the observed power is more than transmitted power, it indicates a collision as shown in figure 3c.
Construction of Ethernet Frame
Ethernet uses packets to send and receive data. A data packet is called a frame as shown in figure 3d.A frame consists of six different parts: First part is the preamble which consists of 7 bytes with 1 & 0 alternatives in this form "10101010". The preamble frame is used for getting circuits to become synchronized with each other. Second part is called SFD (Start Frame Delimiter) and which consists of only Ibyte long and has the form "10101011". The SFD indicates where the first bit of the frame is located. The SFD stops with two consecutive ones to indicate this. Thirdly part is called address field and it has both destination address and source address, the destination address is the address where the message is sent to. The source address is the address from which the massage is sent. Each one of these fields is 6 bytes. Fourth is called Type or length field and consist of 2 bytes, if the value is less than or equal to 1500 decimal, then it is considered to be a length field. If it is greater than or equal to 1536 decimal, then it is considered to be a type field. Fifth is called data field and which can be between 46 bytes and 1500 bytes long. If the data that been sent is shorter than 46 bytes then zero padding method is used. The last field is the FCS (Frame Check Sequence) which is 4 bytes long. This frame is used for checking that the transfer of bits has been error free. The method that is used to verify that there are no errors in the sent data is called CRC (Cyclic Redundancy Check).
Calculation of the CRC: When calculating the CRC, polynomials are used to represent the binary numbers. So, the frame is called M when using the polynomials. The transmitted frame, from destination address to and including the FCS, is called T and looks like in equation.
T = M *x32+ R
Frame that shall be sent, M: x7 + x5 + x4 + x2, m:"10110100"
1101 10110100000 1101 01100100000 1101 00001100000 1101 00000001000 1101 00000000101
Pre-defined polynomial, G: x3 + x2 + 1, g: "1101"
R: x2 + 1;
T: x10 +x8 +x7 +x5 +x2 +1
Figure 4illustrates (a) Block Diagram over HDMI; (b) Time Diagram for data transmission over TMDS; and (c) Zynqxc7z020-1CLG484in accordance with an embodiment of the present disclosure.
HDMI is an interface for transferring video and audio data between two devicesas shown in figure 4a. It is commonly used to connect a computer to a monitor. To minimize the EMI (electromagnetic interference) TMDS is used. It is trying to minimize the number of transitions in the cable. The HDMI source generates data (video, audio) signals. The video and audio data are fed to the HDMI transmitter, which process the signals and converts them to TMDS. Some control and status signals are fed to the HDMI transmitter as well. The HDMI transmitter encodes the signals so that can be sent on the HDMI cable. In the middle is the cable which consists of 19 wires. Each of the 3 channels and the clock channel has 3 wires, one is for shield and the other two are for data transmission. In that two wires the data are inverted to each other.
TMDS and its working principle
TMDS stands for Transition Minimized Differential Signaling and which uses a coding algorithm that is minimizing the transitions in the cable. Each channel has two wires for data transmission in which data are inverted to each other as shown in figure 4b. Through the three channels video, audio and auxiliary data are transmitted in different time periods. To minimize the number of transitions an advanced algorithm is used that convert 8 bits to 10 bits with fewer transitions. With the 10 bits it is possible to have 1024 different combinations. To represent the 256 different types of colors, 460 combinations are used. A color can be represented by at most two combinations and some colors have only one combination. Four combinations are used for control signals. The rest of the combinations are reserved and forbidden, that is 560.The three different modes are used to transmitting data over the TDMS channels. The modes are control period, data island period and video data period where the pixels are sent in the video data period, Audio and Axillary data are delivered in data island period. The audio, auxiliary data are transferred when control period is active. It is used for synchronization or contains a preamble which indicates what type of data that will follow, Video Data Period or Data Island Period.
Design of Ethernet
It deals with the different design aspects of Ethernet and the VHDL code that has been designed for the Ethernet.
Ethernet Hardware and Software
Ethernet controller is available on the Zed board. To communicate with Ethernet controller a kind of Ethernet core is necessary; the core from Open Cores is written in Verilog or VHDL and uses the Wishbone bus protocol to communicate with a module. Viva do was released in 2012 and is Xilinx's next-generation replacement for ISE. With its advent since 2013 there have been no new versions of ISE. All the 7-series FPGA's or newer requires Viva do. However, if you want to work with older FPGA series like Virtex 5 then you have to use ISE only. Viva do very easily superseded ISE with additional features for SOCs high level synthesis and development.
Memory: Zynq consists of a hardened Processing System Memory Interface Unit (MIU). MIU includes static memory modules and dynamic memory controller.
DDR3: It makes a 32 bit interfacing unit and consists of MT4J128M16HA-15E micron and speeds upto 533MHz. DDR3 uses 1.5V SSTL-compatible inputs.
SD Card Interface: It is interfaced by 3.3V and M10 Bank 1/501 is connected to it.
SPI Flash: Zed Board has a 4-bit SPI serial NOR flash. It connects and supports Quad I/O SPI interface and Zynq 7000 AP.
USB OTG: Zed Board implements one in all the two available PS USB OTG interfaces. A TI TUSB1210 Standalone USB Transceiver Chip is used as PHY. This USB port will not power the board.
USB UART: USB UART to a PS UART peripheral is connected as a bridge. In the Zed board USB UART is connected to a USB Micro B i.e J14TE1981584-1.
JTAG: Zed Board provides JTAG functionality connector i.e J15 used DIGILENT programming cables JTAGHS1 and also used in Xilinx Platform cables.
VGA Connecter: TE 4-1734682-2 VGA connecter provides 12-bit color video output.
HDMI output: HDMI Transmitter ADV7511 produces a digital video line to the Zed Board. ADV7511 provides 8-channel 12S and audio S/PDIF.
12S Audio Codec: ADAU1761 Audio Codec is interfaced to Zynq-7000 AP SoC and audio processing which provides digital volume control.
OLED: UG-2832HSWEG04 Inteltronic or Wisechip OLED Display is present on the board. It gives passive-matrix, monochrome display and 128x32 pixel.
Digilent Pmod Compatible Headers: There are five Digilent Pmod compatible headers out of which four Pmod Connectors are connected to Bank 13 and one connected to M10pins in M10 bank 0/500 of PL side.
LPC FMC Connector: It consists of 68 number single ended Input/Output from which 34 are configured into differential pairs. A large number ecosystem is supported which is provided on the Zed Board. It is a single low pin count FMC slot which acts as a plug in modules.
Push Switch: BTN6, A PROG push switch and toggles Zynq PROG_B initiates reconfiguring the PL-subsection with the help of a processor.
Figure 5 illustrates (a) Flow chart of Ethernet; (b) Flow chart of HDMI; and (c) Finite State Machine in accordance with an embodiment of the present disclosure.
Ethernet Core to Ethernet Controller
Communication between Ethernet core and the Ethernet controller are done using a various type of signals. MII (Media Independent Interface) protocol is used to communicate Ethernet core to Ethernet controller. It consists of two parts i.e data interface and management interface. Data interface is used for transmitting and receiving Ethernet frames.
Design of Ethernet - VHDL Code
The sending and receiving of the actual Ethernet frames is done by the on-board Ethernet controller (Figure 5a). To be able to communicate with the controller is quite difficult, so a predesigned core was used. To use a core also speeds up design time. A core from Open Cores was chosen. It was a free core which had a relatively easy protocol to communicate with it, which was Wishbone. To be able to communicate with the Ethernet core via the Wishbone3 protocol a FSM (Finite State Machine) was used. The Finite State
Machine was written in VHDL and contains 103 states. It contains an initialization phase for the Ethernet core. Then it waits for the user to set some switches on. To get it to receive Ethernet frames continuously a switch must be set. Then it will go to a state where it waits until it captures anything on the network. Every time a frame has been received a LED is glow on the board. The frame is checked for its MAC destination address to see if it is sent to the correct device or not.
Design of HDMI
HDMI design deals with the design of the different aspects of HDMI and the VHDL code that has been designed for the HDMI cable (Figure 5b).
HDMI Hardware: (ZedBoard)
The ZedBoard is a development board and evaluation based on Zyn-7000 Extensible Processing Platform. Combining a Cortex-A9 PS contains programmable logic cells with 85000 series7.It contains everything which is required to generate a Linux, Windows, Android, OS/RTOS-based design. Target Applications includes Motor control, Video processing, Embedded ARM processing, Software acceleration, Linux/Android/RTOS development
Design of HDMI - VHDL Code
The sending of HDMI data has been done using example files from Xilinx that were written in Verilog. These files just send out a simple test image to the screen. They were originally designed for DVI cables but it works equally well for HDMI. The Finite State Machine is written in VHDL and consists of 7 states; it starts by requesting pixel data from theDDR2 memory. When it gets the pixel data from the memory it will wait for to place the data on screen. Since the screen is updating pixel by pixel, it is necessary to wait for the screen to update the block of pixels that just has been collected from the DDR2 memory. Before it leaves this state the current position of the pixel block is stored in a register. In the next state the pixel block will be increased by one and a request is sent to the memory for the next pixel data. Then it waits again for the data from the memory. This is how the FSM machine is working for generating and collecting pixels to the screen.
Design of VHDL Code That Handle the Memory
Since an entire image frame cannot be stored in a register in the FPGA, the data is stored in a memory instead (Figure 5c). To communicate with the memory, a core was used to speed up the design time and to be able to use it in an easier method. To control the core a FSM was used. The Finite State Machine was written in VHDL and consists of 13 states. The Finite State Machine starts with an initialization state where it waits for the clock to be synchronized. Then it waits for a read signal. When a read signal is activated, it starts to send a read request to the core with the pixel block counter as an address in the memory. When the core has collected the data from the memory it will send it out so it can be collected by a register in the FSM. A signal is indicating that data has been read from the memory and is available for the HDMI Finite State Machine to catch for a brief period of time. Then it returns to the wait state and waits for new commands.
Figure 6illustrates(a) AXI Ethernet Subsystem; and (b)AXI HDMIin accordance with an embodiment of the present disclosure.
ZedBoard Evaluation Kit has been used as hardware and software Xilinx Vivado 18.2 which is used for synthesis and implementation is for designing AXI Ethernet subsystem and HDMI which is shown in the figure 6b. The language which is used is VHDL.IP is also modified according to zedboard specification and requirement. The block diagram which is generated in the operation process as well as open implementation design is shown in the following figure 6a and figure 6b with the setup. ZC-702 board is the Zynq board (Zed board Xc7z020clg484-1 while selecting the board type in the software Xilinx Vivado which will be used.
The drawings and the forgoing description give examples of embodiments. Those skilled in the art will appreciate that one or more of the described elements may well be combined into a single functional element. Alternatively, certain elements may be split into multiple functional elements. Elements from one embodiment may be added to another embodiment. For example, orders of processes described herein may be changed and are not limited to the manner described herein. Moreover, the actions of any flow diagram need not be implemented in the order shown; nor do all of the acts necessarily need to be performed. Also, those acts that are not dependent on other acts may be performed in parallel with the other acts. The scope of embodiments is by no means limited by these specific examples. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible. The scope of embodiments is at least as broad as given by the following claims.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any component(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or component of any or all the claims.
Claims (10)
1. A system for IP's for ethernet and HDMI using Xilinx Viva do for internet of things application, said system comprises: an ethernet module to handle communication to send and receive data between devices via an ethernet controller; a HDMI module to transfer video and audio data between two devices via a HDMI buffer; and a memory module to handle communication with said ethernet and HDMI and a DDR2 SRAM (Double Data Rate Synchronous Dynamic Random-Access Memory) memory on a board.
2. The system as claimed in claim 1, wherein said ethernet uses carrier sense multiple access with collision detection i.e. CSMA-CD protocol while transmitting with data.
3. The system as claimed in claim 1, wherein sending and receiving of actual Ethernet frames is done by on-board Ethernet controller.
4. The system as claimed in claim 1, comprises a predesigned core to communicate with said Ethernet controller, wherein an FSM (Finite State Machine) is used to communicate with Ethernet core via a Wishbone3 protocol.
5. The system as claimed in claim 4, wherein said finite state machine is written in VHDL and contains 103 states, and an initialization phase for said Ethernet core.
6. A method for IP's for ethernet and HDMI using Xilinx Viva do for internet of things application, said method comprises: handling communication using an ethernet module to send and receive data between devices via an ethernet controller; transferring video and audio data between two devices using a HDMI module via a HDMI buffer; and handling communication with said ethernet and HDMI and a DDR2 SRAM (Double Data Rate Synchronous Dynamic Random-Access Memory) memory on a board through a memory module.
7. The method as claimed in claim 6, wherein steps for frame received indication for saving frame in memory comprises: waiting for a user to set some switches on; setting a switch to get it to receive Ethernet frames continuously; going to a state where it waits until it captures anything on network; glowing a LED upon receiving of a frame; checking frame for its MAC destination address to see if it is sent to correct device or not; and indicating receiving of frame for saving frame in memory.
8. The method as claimed in claim 6, wherein steps for transmitting pixel on three channels on HDMI comprises: requesting pixel data from memory and waiting for pixel data memory; waiting for right time to display pixel data on a screen; dividing pixels in three parts one for each color; and transmitting pixel on three channels on HDMI.
9. The method as claimed in claim 6, wherein starting finite state machine with an initialization state and thereby waiting for a clock to be synchronized; waiting for a read signal and thereafter sending a read request to core with pixel block counter as an address in said memory upon activating said read signal; wherein said core collects data from said memory and thereupon informs to collect by a register in said FSM; wherein a signal is indicating that data is read from said memory and is available for said HDMI Finite State Machine to catch for a brief period of time; and returning to a wait state and waiting for new commands.
10. The method as claimed in claim 6, wherein video and audio data are fed to HDMI transmitter, which process signals and converts them to TMDS.
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