AU2021101243A4 - A multilevel image segmentation hardware - Google Patents

Abstract

A MULTILEVEL IMAGE SEGMENTATION HARDWARE The present invention presents hardware to implement multilevel thresholding of gray scale images. The basic principle of the invention is based on the fact that the intensity distribution 5 in a gray scale image approximated by a multilevel sigmoidal function. A multilevel sigmoidal function is an extension of the standard sigmoidal function which comprises multiple lobes/levels to represent transitions from one gray level to another. Such function faithfully used to approximate the gray level transitions in a gray level image based on a chosen number of thresholds which in turn determine the different transition lobes/levels of 10 the function. This function possesses the properties of continuity and differentiability. The invention has the variety of applications which include Video segmentation, Data Clustering, Multilevel thresholding of images, Big data analysis, Satellite image analysis etc. (FIG. 1 will be the reference figure) 15 BLOCKAVGVALUEIN FIXEDVALUE_OUT NOOFSEGMENTVALUEIN VALID_OUT 20 System VALIDIN 25 CLOCK_IN RESET_N_IN FIG. 1 Top level block diagram - 16-

Description

FORM2 THE PATENTS ACT 1970 39 OF 1970

& THE PATENT RULES 2003 COMPLETE SPECIFICATION (SEE SECTIONS 10 & RULE 13)

1. TITLE OF THE INVENTION

A MULTILEVEL IMAGE SEGMENTATION HARDWARE

2. APPLICANTS (S) NAME NATIONALITY ADDRESS

1. Siddhartha IN Dhakhineswari Apartment. Flat 301, 3rd Floor, B. T. Road, 8 (Hold), Panihati, Kolkata 700 114, Bhattacharyya West Bengal, India

2. Abhishek Basu IN MIG(U) 17/10, Birati Housing Estate, M.B.Road, P.O. +P.S.-Nimta Kolkata, West Bengal, India Pin 700049 3. Sourav De IN No. 2, Dhobapara Lane, Jhapantala, P.O. Burdwan Rajbati, Burdwan, West Bengal, India, Pin 713104

4. Jan Platos CZ Eviena Rosick6ho 1074/6, 72100 Ostrava Svinov, Czech Republic Europe 5. Vaclav Snasel CZ VSB-Technical University of Ostrava 17. listopadu 2172/15, 70800 Ostrava-Poruba, Czech Republic, Europe

6. Leo Mrsi6 HR Vukovarska 20, Ivanic Grad 10310, Croatia, Europe

3. PREAMBLE TO THE DESCRIPTION

COMPLETE SPECIFICATION

The following specification particularly describes the invention and the manner in which it is to be performed

A MULTILEVEL IMAGE SEGMENTATION HARDWARE SPECIFICATION TECHNICAL FIELD

[0001] The present disclosure relates to a process for image segmentation to segregate an image into several distinct homogenous regions by multilevel thresholding and in particular to the multilevel image segmentation hardware.

BACKGROUND

[0002] Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.

[0003] The Segmentation and localization of homogeneous objects in an image still remains a challenging proposition due to the complexity and uncertainty of the intensity distributions therein. A simple binary segmentation is equivalent to background subtraction. However, the problem of segmentation poses challenge when it comes to segmentation of multilevel and color images mainly due to the wide distribution of colors of the color intensity gamut.

[0004] Thresholding is treated as the simplest method for image segmentation. Various well-known thresholding schemes are existent, viz., Otsu's method, minimum error thresholding, and methods based on the entropy of the histogram. Interested readers may refer to the literature for a collection of thresholding techniques.

[0005] Efforts have been made Chieh-Chi Kao et al., "Automatic object segmentation with salient color model", 2011 IEEE International Conference on Multimedia and Expo (ICME), IEEE, 11 July 2011, pages 1 - 6, DOI: 10.1109/ ICME.2011.6011909, ISBN: 978-1-61284-348-3 describes a combined detection of (colour) saliency and segmentation without user interaction. Colour models and seeds are derived from a saliency model to avoid user input. Finally, the image is segmented using the MinCut algorithm.

[0006] In Zhaohui Wang et al., "Automatic Object Extraction in Nature Scene Based on Visual Saliency and Super Pixels", 26 October 2012, Artificial Intelligence and Computational Intelligence, Springer, Berlin, Heidelberg, pages 547 - 554, ISBN: 978-3 642-33477-1 describes an automatic colour-based salient object extraction in natural scenes further employing a graph cut algorithm. Over-segmentation is addressed with an improved watershed algorithm, before the final segmentation is obtained from cutting a weighted, undirected graph.

[0007] In some embodiments, the numbers expressing quantities or dimensions of items, and so forth, used to describe and claim certain embodiments of the invention are to be understood as being modified in some instances by the term "about." Accordingly, in some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.

[0008] The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. "such as") provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.

OBJECTS OF THE INVENTION

[0009] It is an object of the present disclosure, which provides a hardware for multilevel image segmentation that it provides simplest method for image segmentation.

[0010] It is an object of the present disclosure which provides a method that provides minimum error thresholding.

[0011] It is an object of the present disclosure which provides a hardware for thresholding of gray scale images.

SUMMARY

[0012] The present concept of the present invention is directed towards a hardware to implement multilevel thresholding of gray scale images. The basic principle of the work may be based on the fact that the intensity distribution in a gray scale image can be approximated by a multilevel sigmoidal function. A multilevel sigmoidal function may be an extension of the standard sigmoidal function which comprises multiple lobes/levels to represent transitions from one gray level to another. Such a function may be faithfully used to approximate the gray level transitions in a gray level image based on a chosen number of thresholds which in turn determine the different transition lobes/levels of the function. This function possesses the properties of continuity and differentiability.

[0013] In an aspect, the present invention further discloses the techniques for the FPGA implementation of segmentation of gray scale image is disclosed. The technique include concept of look up table to generate segmented image based on input lobe value from preloaded lobe value memory.

[0014] One should appreciate that although the present disclosure has been explained with respect to a defined set of functional modules, any other module or set of modules can be added/deleted/modified/combined, and any such changes in architecture/construction of the proposed system are completely within the scope of the present disclosure. Each module may also be fragmented into one or more functional sub-modules, all of which also completely within the scope of the present disclosure.

[0015] Various objects, features, aspects and advantages of the inventive subject matter will become more apparent from the following detailed description of preferred embodiments, along with the accompanying drawing figures in which like numerals represent like components.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0001] FIG. 1 illustrates a Top Level Block Diagram of the invention in accordance with an embodiment of the present disclosure.

[00171 FIG. 2 illustrates an Internal Architecture of System in accordance with an embodiment of the present disclosure.

[0018] FIG. 3 illustrates a 16 Segment lobe value Memory in accordance with an embodiment of the present disclosure.

[0002] FIG. 4 illustrates an 8 Segment lobe value Memory in accordance with an embodiment of the present disclosure;

[0019] FIG. 5 illustrates a 6 Segment lobe value Memory in accordance with an embodiment of the present disclosure.

[00031 FIG. 6 illustrates a 4 Segment lobe value Memory in accordance with an embodiment of the present disclosure.

[0004] FIG. 7 illustrates a lobe value Memory in accordance with an embodiment of the present disclosure

[0005] FIG. 8 illustrates a Switch Box connection Controller Memory in accordance with an embodiment of the present disclosure.

[00061 FIG. 9 illustrates an Evaluation Block in accordance with an embodiment of the present disclosure.

[00071 FIG. 10a illustrates a Top Level view in accordance with an embodiment of the present disclosure.

[00081 FIG. 10b illustrates an RTL View in accordance with an embodiment of the present disclosure.

[00091 FIG. 11 illustrates an Output for block average value 200 with no of segment 8.

[0010] FIG. 12 illustrates an Output for block average value 200 with no of segment 16.

[0011] FIG. 13 illustrates an Output for block average value 200 with no of segment 6.

[0012] FIG. 14 illustrates an Output for block average value 200 with no of segment 4.

[00131 FIG. 15 illustrates a Port list and their functionality.

[0014] FIG. 16 illustrates a device utilization summary.

[0020] It should be noted that the figures are not drawn to scale, and the elements of similar structure and functions are generally represented by like reference numerals for illustrative purposes throughout the figures. It should be noted that the figures do not illustrate every aspect of the described embodiments and do not limit the scope of the present disclosure.

[0021] Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the present embodiment when taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION

[0022] Aspects of the present disclosure relate to a hardware for multilevel thresholding of gray scale images. It is inferred that the foregoing description is only illustrative of the present invention, and it is not intended that invention be limited or restrictive thereto. Many other specific embodiments of the present invention will be apparent to one skilled in the art from the foregoing disclosure. All substitutions, alterations and modifications of the present invention which comes within the scope of the following claims are to which the present invention is readily susceptible without departing from the spirit of the invention. The scope of the invention should therefore be determined not with reference to appended claims along with the full scope of equivalents to which such claims are entitled.

[0023] Embodiments of the present invention may be provided as a computing device, which may include one or more storage medium tangibly embodying thereon instructions and unique identities of the device, the instruction may be used to prevent the unauthorized user to alter/erase the unique identities of the device. The storage mediums may include, but is not limited to, semiconductor memories, such as ROMs, PROMs, random access memories (RAMs), programmable read-only memories (PROMs), erasable PROMs (EPROMs), electrically erasable PROMs (EEPROMs), flash memory, or other type of media/machine-readable medium suitable for storing unique ID(s) of the device and electronic instructions (e.g., computer programming code, such as software or firmware).

[00241 If the specification states a component or feature "may", "can", "could", or "might" be included or have a characteristic, that particular component or feature is not required to be included or have the characteristic.

[0025] Although the present invention has been described with relation noise reduction and channel noise management in cognitive radio, it should be appreciated that the same has been done merely to illustrate the invention in an exemplary manner and any other purpose or function for which the explained structure or configuration can be used, is covered within the scope of the present disclosure.

[00261 Exemplary embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those of ordinary skill in the art. Moreover, all statements herein reciting embodiments of the invention, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents as well as equivalents developed in the future (i.e., any elements developed that perform the same function, regardless of structure).

[00271 The following is a detailed description of embodiments of the disclosure depicted in the accompanying drawings. The embodiments are in such detail as to clearly communicate the disclosure. However, the amount of detail offered is not intended to limit the anticipated variations of embodiments; on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.

[00281 Each of the appended claims defines a separate invention, which for infringement purposes is recognized as including equivalents to the various elements or limitations specified in the claims. Depending on the context, all references below to the

"invention" may in some cases refer to certain specific embodiments only. In other cases, it will be recognized that references to the "invention" will refer to subject matter recited in one or more, but not necessarily all, of the claims.

[0029] Various terms as used herein are shown below. To the extent a term used in a claim is not defined below, it should be given the broadest definition persons in the pertinent art have given that term as reflected in printed publications and issued patents at the time of filing.

[00301 In an embodiment of the present disclosure relates to processes for the execution of multilevel thresholding of gray scale images along with FPGA implementation. The processes include the thresholding mechanism in a multilevel incarnation to achieve segmentation of gray level images. The process resorts to a set of fixed and predetermined threshold values. It has been assumed that the intensity distribution in a gray scale image can be approximated by a multilevel sigmoidal function. The multilevel sigmoidal function can be a functional extension of the sigmoidal function widely used for binary thresholding. The multilevel function comprises multiple lobes/levels to represent transitions from one gray level to another. This function used to approximate the gray level transitions in a gray level image based on a chosen number of thresholds which in turn determine the different transition lobes/levels of the function. Moreover, the function possesses the properties of continuity and differentiability.

[0015] In an aspect, FIG. 1 is the entity of top level block which indicates FPGA architecture offered here by means of port list & functionality.

[0016] In another aspect of the present invention, FIG. 15 is the elaboration of different port list used in entity through port direction, port width and port functionality.

[0017] In yet another aspect ofthe present invention, The top level block diagram which accept average value of corresponding image block in Grey scale format along with number of Lobe or Segment values (values are 4/6/8 or 16). The system can accept inputs when the validin pin will get a high value and when the valid in pin input value is low the system will start processing the data to get a single fixed value for the corresponding image block. After getting segment value information, default lobe values get loaded into Lobe value memory by Switch box connection controller form selected Segment lobe value memory. Ultimately lobe value form memory can be transferred to evaluation block one by one based on assessment requirement and depend on average value of the image block the final fixed gray value selected. When the output will contain data values for further processing to other interfaces, the valid out pin can produce high value as acknowledgment of valid data otherwise it produce low value.

[0018] In yet another aspect of the present invention, FIG. 2 is the internal architecture of the invention. The architecture comprise seven different components named as "16 Segment lobe value Memory", "8 Segment lobe value Memory", "6 Segment lobe value Memory"," 4 Segment lobe value Memory" "," Lobe value Memory", "," Switch Box Connection Controller" and "Evaluation Block" under system entity and these components are portmapped according to the requirement.

[0031] In yet another aspect of the present invention, FIG. 3 is the 16 Segment lobe value Memory will hold the sixteen different lobe values in binary byte format. These values indicate, one block average value can be replaced by one of them after evaluation. When number of segments are 16, this memory values can be transferred and loaded into lob value memory by switch box controller.

[0019] In yet another aspect of the present invention, FIG. 4 is the 8 Segment lobe value Memory will hold the eight different lobe values in binary byte format. These values indicate, one block average value may be replaced by one of them after evaluation. When number of segments are 8, this memory values can be transferred and loaded into lob value memory by switch box controller.

[0032] In yet another aspect of the present invention, FIG. 5 is the 6 Segment lobe value Memory will hold the six different lobe values in binary byte format. These values indicate, one block average value can be replaced by one of them after evaluation. When number of segments are 6, this memory values can be transferred and loaded into lob value memory by switch box controller.

[00331 In yet another aspect of the present invention, FIG. 6 is the 4 Segment lobe value Memory will hold the four different lobe values in binary byte format. These values indicate, one block average value can be replaced by one of them after evaluation. When number of segments are 4, this memory values will be transferred and loaded into lob value memory by switch box controller.

[0034] In yet another aspect of the present invention, FIG. 7 presenting lobe value memory that will hold the selected segment value data based on the no of segment value pass to switch box connection controller. In this process maximum 16 values can be kept within the memory as highest segment value is 16. When less than 16 segment value has been received only lower section of the memory store the data. Rest memory locations are not used during operation of lower segment values. If segment value is 4, then 0 to 3 locations are filled up with the data from 4 Segment lobe value Memory and other locations are holding garbage value. When validin pin value is high the write controller will write all the supplied values to memory and when the value is low read controller can start working. During reading operation, data get transferred to evaluation block for decision making.

[00351 In yet another aspect of the present invention, FIG. 8 is the process of establishing the connection between Lobe value memory and segment lobe value memories can be performed by switch box connection controller. Depending on the number of segment value one of four segment lobe value memories get identified and data transferred to lobe value memory.

[00361 In yet another aspect of the present invention, FIG. 9 is the evaluation block which is the final one which makes the decision process about fixed value for corresponding image block.

[00371 In yet another aspect of the present invention, the evaluation process the block average value can be stored into average value register and lobe value selector sends supplied segment value data one by one to magnitude comparator. Based on the output of magnitude comparator, decision making block finds out the fixed value for the block. Once the decision has been made about fixed value the valid-out pin become high value else the value can be low and the operation about decision making get continues. Once decision of corresponding block is finalized, the system can get ready for the next block average value input till the entire image block complete.

[0020] In yet another aspect of the present invention, FIG. 10, FIG. 11, FIGURE. 12, FIG. 13, FIG. 14 and FIG. 16 provides result of FPGA Implementation and HDL Simulation process. To conduct the FPGA implementation and HDL simulation Xilinx ISE 13.2 has been used, FPGA Family: Artix7, Device: XC7A30T and Package: CSG324.

[0021] In yet another aspect of the present invention, the top level view and RTL view of the invention given in FIG. 10 and device utilization summary presented in FIG. 16.

[0022] In yet another aspect of the present invention, the performance of the process has been evaluated by HDL simulation. Different block average value and lobe/segment value has been feed as simulation input to the system and the approximated value along with validity checked from output. Form FIG. 11 to FIG. 14 that are clear that after getting the average value and lobe number information, the system has produced approximated value and high signal at valid-out pin to indicate valid data present. For better understanding the values can be converted to unsigned decimal during representation at output waveforms.

[0038] While the foregoing describes various embodiments of the invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof. The scope of the invention is determined by the claims that follow. The invention is not limited to the described embodiments, versions or examples, which are included to enable a person having ordinary skill in the art to make and use the invention when combined with information and knowledge available to the person having ordinary skill in the art.

[00391 Thus, the scope of the present disclosure is defined by the appended claims and includes both combinations and sub-combinations of the various features described hereinabove as well as variations and modifications thereof, which would occur to persons skilled in the art upon reading the foregoing description.

Claims (4)

We Claim:

1. A process (100) for implementing a multilevel image/data segmentor based on the multilevel sigmoidal function image approximator, said process involving the steps of:

selecting appropriate threshold points in the Image feature space;

designing activation function for threshold selection;

outlining the activation function to get uniform thresholding mechanisms;

incorporating the image context information in the thresholding process.

2. The process as claimed in claim 1, wherein the threshold points in the Image feature space are pre-determined, wherein the pre-determined threshold points determine the different transition lobes/levels of the function.

3. The process as claimed in claim 1, wherein the activation function is the sigmoidal function, wherein the sigmoidal function is a functional extension of the sigmoidal function widely used for binary thresholding.

4. The process as claimed in claim 1, wherein the thresholding process the used for determining the grey level transitions in a gray level image based on a chosen number of thresholds which in turn determine the different transition lobes/levels of the function.

Application no.: Total no. of sheets: 16

Applicant name: Page 1 of 16 Mar 2021 2021101243

Figure 1: Top Level Block Diagram

Application no.: Total no. of sheets: 16

Applicant name: Page 2 of 16 Mar 2021 2021101243

Figure 2: Internal Architecture of System

Application no.: Total no. of sheets: 16

Applicant name: Page 3 of 16 Mar 2021 2021101243

Figure 3: 16 Segment lobe value Memory

Application no.: Total no. of sheets: 16

Applicant name: Page 4 of 16 Mar 2021 2021101243

Figure 4: 8 Segment lobe value Memory

Application no.: Total no. of sheets: 16

Applicant name: Page 5 of 16 Mar 2021 2021101243

Figure 5: 6 Segment lobe value Memory

Application no.: Total no. of sheets: 16

Applicant name: Page 6 of 16 Mar 2021 2021101243

Figure 6: 4 Segment lobe value Memory

Application no.: Total no. of sheets: 16

Applicant name: Page 7 of 16 Mar 2021 2021101243

Figure 7: lobe value Memory

Application no.: Total no. of sheets: 16

Applicant name: Page 8 of 16 Mar 2021 2021101243

Figure 8: Switch Box connection Controller

Application no.: Total no. of sheets: 16

Applicant name: Page 9 of 16 Mar 2021 2021101243

Figure 9: Evaluation Block

Application no.: Total no. of sheets: 16

Applicant name: Page 10 of 16 Mar 2021 2021101243

a.

b. Figure 10: a. Top Level view b. RTL View

Application no.: Total no. of sheets: 16

Applicant name: Page 11 of 16 Mar 2021 2021101243

BLOCK_AVG_VALUE_IN= 200 (“11001000”), NO_OF_SEGMENT_VALUE_IN=8 (“01000”)

Figure 11: Output for block average value 200 with no of segment 8

Application no.: Total no. of sheets: 16

Applicant name: Page 12 of 16 Mar 2021 2021101243

BLOCK_AVG_VALUE_IN= 200 (“11001000”) NO_OF_SEGMENT_VALUE_IN=16 (“10000”)

Figure 12: Output for block average value 200 with no of segment 16

Application no.: Total no. of sheets: 16

Applicant name: Page 13 of 16 Mar 2021 2021101243

BLOCK_AVG_VALUE_IN= 200 (“11001000”) NO_OF_SEGMENT_VALUE_IN=6 (“00110”)

Figure 13: Output for block average value 200 with no of segment 6

Application no.: Total no. of sheets: 16

Applicant name: Page 14 of 16 Mar 2021 2021101243

BLOCK_AVG_VALUE_IN= 200 (“11001000”) NO_OF_SEGMENT_VALUE_IN=4 (“00100”)

Figure 14: Output for block average value 200 with no of segment 4

Application no.: Total no. of sheets: 16

Applicant name: Page 15 of 16 Mar 2021 2021101243

Port-Name Direction Width Functionality BLOCK_AVG_VALUE_IN In 8 Bit Grey scale Value which indicates the average value of corresponding image block. VALID_IN In 1 Bit Active high signal for enabling the system for accepting BLOCK_AVG_VALUE_IN input. System does not accept any BLOCK_AVG_VALUE_IN input if the signal value is low. NO_OF_SEGMENT_VALUE_IN In 5 Bit Indicate number of Lobe or Segment. Values lie between 4 to 16 and particular values are 4,6,8 & 16 CLOCK_IN In 1Bit Positive edge input for valid operation(global signal) RESET_N_IN In 1Bit Active low signal to clear all registers(global signal) FIXED_VALUE_OUT Out 8 Bit Grey scale Value which indicates the fixed value for the corresponding image block. VALID_OUT Out 1Bit Active high signal to indicate valid data present in FIXED_VALUE_OUT

FIG. 15 Port List and their functionality

Application no.: Total no. of sheets: 16

Applicant name: Page 16 of 16 Mar 2021 2021101243

Device Utilization Summary (estimated values) [-] Logic Utilization Used Available Utilization Number of Slice Registers 171 42000 0% Number of Slice LUTs 289 21000 1% Number of fully used LUT-FF pairs 76 384 19% Number of bonded IOBs 25 210 11% Number of BUFG/BUFGCTRLs 1 32 3%

FIG. 16 Device utilization summary