AU2011201247B2

AU2011201247B2 - Grid connectable inverter with ripple control signal rejection

Info

Publication number: AU2011201247B2
Application number: AU2011201247A
Authority: AU
Inventors: Dale John Butler
Original assignee: LEOMON Pty Ltd
Current assignee: LEOMON Pty Ltd
Priority date: 2010-03-24
Filing date: 2011-03-21
Publication date: 2015-06-11
Anticipated expiration: 2031-03-21
Also published as: AU2011201247A1

Abstract

Abstract Power inverters that are connected to the grid and which tend to shunt the grid's ripple control signal will have an adverse effect upon the ripple control system as they may attenuate the control signal below the relay sensitivity of devices such as hot water heaters. In order to address this problem there is provided a switch mode device having an output terminal for connection to an electrical network conveying a first signal of predetermined frequency and a second signal of a frequency falling within a predetermined range, the switch mode device being configured to produce a signal at the predetermined frequency at the output terminal and including: a processor coupled to a current sensor for sensing current through the terminal and arranged to cause switching of output switches coupled to said terminal; and a memory storing a firmware product including instructions for execution by the processor, to determine the second signal, and instructions to cause the processor to operate the output switches to apply an anti-phase version of the second signal to the terminal. +Dc Source - C1 L 1 L2 point of Coupling -Dc Source Figure 4 Network voltatge (235 V rms typical) + Ripple control signal 1-12V rms Current Coupling impedance (0.15 Ohm @ 50 Hz) Inverter measurement (approaches infinity as the current at 281 Hz is reduced towards zero @ 281 Hz)) Figure 5

Description

AUSTRALIA PATENTS ACT 1990 COMPLETE SPECIFICATION GRID CONNECTABLE INVERTER WITH RIPPLE CONTROL SIGNAL REJECTION The following statement is a full description of this invention including the best mode of performance known to the applicant: 1 GRID CONNECTABLE INVERTER WITH RIPPLE CONTROL SIGNAL REJECTION 5 TECHNICAL FIELD Embodiments of the present invention relate to pulse width modulated (PWM) inverters used for supplying power into electricity distribution grids. 10 BACKGROUND In a number of countries, including Australia, power utilities make use of ripple control to remotely control consumer loads such as domestic hot water systems. Ripple control involves the power utility superimposing a ripple 15 control signal of, for example, 281 Hz at 6-8 Volts RMS over the AC power supply, which in Australia is provided 50Hz, as opposed to 60Hz in the USA. The ripple control signal frequencies are deliberately chosen to bear no relation to the harmonics of the power AC power supply signal that are typically encountered in distribution networks. Consumer appliances that 20 respond to the ripple control signal are fitted with a control relay that typically has a sensitivity of around 1 Volt RMS. Any impedance that is connected to the grid and tends to shunt the ripple control signal will have an adverse effect upon the ripple control system as it may attenuate the control signal below the relay sensitivity. 25 Figure 1 shows curves for the 50Hz supply signal, ripple control signal, and random and harmonic noise on a 50Hz electricity supply line. Figure 2 is a high level block diagram of a prior art DC-AC inverter. It will be 30 noted that the inverter includes a low pass LC output filter. The LC filter has a capacitive pole so that it presents a low impedance to current injected into its output terminal at frequencies that are substantially higher than the grid supply frequency. Typically a low value for C will be 2 uF, which presents an impedance of 1.59 kO at 50 Hz. At a ripple control frequency of 281 Hz, the 2 impedance that C presents drops to 2830. Thus, if there is any significant impedance in the line then there will be some attenuation of the ripple signal. When the capacitor is included in the output of an inverter where the PWM 5 frequency is high (say 100 kHz) the inductance in the filter may be only 400uH, which presents an impedance of only 706mQ at 281 Hz. Since the output impedance of the inverter switching section is essentially zero at all frequencies other than the 50 Hz fundamental, the output terminals of the switching section of a high frequency inverter present an impedance to the 10 ripple control signal that is close to zero and is completely defined by the filter inductance. It may be noted that it is this characteristic that makes a sinusoidal inverter into an effective harmonic filter. Typically the inverter will be connected to the network with a coupling impedance of about 5%. This means that for a 20 kVA inverter the coupling impedance will be 0.145 0 (for 15 a value of C of 460 uH) at 50 Hz and 812 mO at 281 Hz. Thus there exists a very low impedance path to attenuate the ripple control signal, which is highly undesirable. In order to achieve regulation in a PWM inverter it is usual to control the "form 20 factor", i.e. the phase of the switching pulses, and hence the RMS value of the output voltage. This is usually done by having a feedback circuit as shown in Figure 3 so that the controller can sense that the load on the inverter's output has increased. The controller is configured to respond to the increased load by increasing the width of the pulses that turn on the switches. 25 Figure 4 illustrates the circuit of one class of inverter at a lower level to that of Figure 2. The two switches, S1 and S2, which are typically implemented by MOSFETs or IGBTs, alternately connect to the large low impedance capacitors C1 and C2 and thus effectively ground the left hand side of L1. 30 Switches S1 and S2 are controlled by a pulse width modulator to produce a pure 50Hz sine wave on the capacitor C3.

3 Since switches S1 and S2 are controlled by the pulse width modulator to produce a pure 50Hz sine wave on the capacitor C3, the inverter appears to the incoming fundamental wave (i.e. waveform 1 of Figure 1) as an open circuit. However, to the ripple signal, noise and any harmonics, the inverter is 5 effectively a short circuit and those signals are severely attenuated. In the case of the noise and harmonics this is a beneficial phenomenon, but as previously explained, attenuation of the ripple control signals constitutes a problem because it jeopardizes the reliability of the ripple control system. 10 It is an object of the present invention to provide an improved means and method for addressing the above problem. SUMMARY OF THE INVENTION According to a first aspect of the invention there is provided a switch 15 mode device having an output terminal for connection to an electrical network conveying a first signal of predetermined frequency and a second signal of a frequency falling within a predetermined range, the switch mode device being configured to produce a signal at the predetermined frequency at the output terminal and including: 20 a first circuit assembly to detect the second signal; and a second circuit assembly responsive to the first assembly and arranged to operate output switches of the switch mode device to apply a signal in anti-phase to the second signal at the output terminal; wherein the first circuit assembly includes a difference circuit to assist 25 in detecting the second signal. Typically the first signal that is conveyed by the electrical network is an electricity distribution power signal with, for example, a predetermined frequency of 50Hz or 60Hz. 30 Typically the second signal that is conveyed by the electrical network is a ripple control signal.

4 Preferably the first circuit assembly includes a current sensor to produce a signal corresponding to current through the output terminal. The first circuit assembly may include an analog to digital converter for 5 digitizing said signal of the current sensor. Preferably the first circuit assembly further includes an RMS current calculator coupled to the current sensor, or to the analog to digital converter, to generate a signal indicating an RMS current value for said current sensor 10 signal. In one embodiment the first circuit assembly further includes an AC signal reference generator responsive to the RMS current calculator and arranged to produce an AC signal having an RMS value corresponding to the 15 RMS current value. In said embodiment the difference circuit is responsive to the current sensor and to the AC signal reference generator to generate a difference signal indicating a difference of the AC signal and the current due to the 20 second signal. Preferably the first circuit assembly includes a bandpass filter responsive to the difference circuit to bandpass filter said difference signal over the predetermined range. 25 The first circuit assembly may further include a frequency extraction circuit responsive to the bandpass filter and arranged to produce a frequency signal indicating a frequency of the difference signal. 30 The first assembly may also include an amplitude extraction circuit responsive to the bandpass filter and arranged to produce an amplitude signal indicating an amplitude of the difference signal.

5 In said embodiment the second circuit assembly further includes a signal inversion circuit to produce an inverted signal corresponding to an inversion of the bandpass filtered signal. 5 Preferably the signal inversion circuit is coupled to respective outputs of the frequency extraction circuit and the amplitude extraction circuit and is arranged to produce the inverted signal based on the amplitude signal and on the frequency signal. 10 In said embodiment the second circuit assembly includes a pulse width modulator controllable by the signal inversion circuit and arranged to generate control signals for controlling said power switches for applying current through the output terminal to prevent attenuation of the ripple control signal. 15 According to a further aspect of the present invention there is provided a method for operating a switch mode device having an output terminal connected to a power distribution network to prevent attenuation of a ripple control signal originating in said distribution network, said method comprising the steps of; 20 determining the ripple control signal by digitizing a signal sensed at the output terminal processing the digitized output terminal signal to compute a sinusoidal reference signal corresponding to a power signal component of the signal at the output terminal; and taking the difference of the digitized output terminal signal and the 25 reference signal for determining the ripple control signal; and; operating output switches of the switch mode device to apply an anti phase ripple control signal through the terminal to thereby reject said ripple control signal. 30 According to a further aspect of the present invention there is provided a switch mode device having an output terminal for connection to an electrical network conveying a first signal of predetermined frequency and a second signal of a frequency falling within a predetermined range, the switch mode 6 device being configured to produce a signal at the predetermined frequency at the output terminal and including: a processor coupled to a current sensor for sensing current through the terminal and arranged to cause switching of output switches coupled to said 5 terminal; and a memory storing a firmware product including instructions for execution by the processor, to determine the second signal by processing a digitized output terminal signal to compute a sinusoidal reference signal corresponding to a power signal component of the signal at 10 the output terminal; and taking the difference of the digitized output terminal signal and the reference signal for determining the ripple control signal; and instructions to cause the processor to operate the output switches to apply an anti-phase version of the second signal to the terminal. 15 According to another aspect of the present invention there is provided an inverter for applying power to an electrical power distribution network including: a pulse width modulator; and 20 a sensor for detecting a ripple control signal in said distribution network; wherein the pulse width modulator is responsive to the current sensor for increasing the impedance of the inverter presented to the network at the ripple frequency. 25 BRIEF DESCRIPTION OF THE DRAWINGS Preferred features, embodiments and variations of the invention may be discerned from the following Detailed Description which provides sufficient 30 information for those skilled in the art to perform the invention. The Detailed Description is not to be regarded as limiting the scope of the preceding Summary of the Invention in any way. The Detailed Description will make reference to a number of drawings as follows: 7 Figure 1 is a graph showing waveforms present on an electricity distribution supply network. Figure 2 is a high level diagram of a prior art PWM inverter. Figure 3 is a high level diagram of a prior art PWM inverter with 5 regulation feedback. Figure 4 is a simplified schematic diagram of an output side of a prior art PWM inverter. Figure 5 is a high level diagram of PWM inverter according to an embodiment of the present invention. 10 Figure 6 is a block diagram of a PWM inverter according to a preferred embodiment of the present invention. Figure 7 is a flowchart of a method according to a preferred embodiment of the present invention. Figure 8 is graph showing a waveform being the summation of a mains 15 supply signal, a ripple control signal and noise. Figure 9 is a graph showing a ripple control signal waveform and a random noise waveform. Figure 10 is a graph showing a ripple control signal waveform. Figure 11 is a graph showing a ripple control signal waveform and an 20 anti-ripple control signal waveform. Figure 12 is a block diagram of a PWM inverter according to a further embodiment of the present invention. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 25 Figure 5 is a high level diagram of an inverter according to a preferred embodiment of the invention whereas Figure 6 is a lower level and more detailed block diagram of the preferred embodiment of the inverter. 30 With reference to Figure 6, the inverter includes transistor switches 30 and 32, coupled between respective +DC and -DC supply rails and to an LCL filter network of inductor L1, capacitor C1 and inductor L2.

8 Transistor switches 30 and 32 are driven by respective drive circuits 34 and 36 which are in turn responsive to the PW modulator 38 of digital signal processor 40. 5 The DSP 40 includes a computational core 52 and memory 54 that stores a firmware product 51 comprised of executable instructions that will be described shortly. DSP 40 also includes onboard analog to digital converters (ADCs) 50A, 50B 10 and 50C. ADC's 50A and 50C are coupled to either side of L2 via buffer circuits 46A and 46C and low pass filters 48A and 48C respectively. The input side of ADC 50B is coupled to a current transducer 56, which is placed in series with the output of the inverter, via buffer circuit 46B and low pass filter 48B. The current transducer 56 is of sufficient bandwidth to pick up all 15 the ripple frequencies of interest. The firmware product 51 that is stored in the DSP's memory 54 includes instructions for the PW modulator 38 to generate switching signals for transistor switches 30 and 32 to generate a sine wave output of the required 20 frequency and output, e.g. 240V at 50Hz. As the inverter operates it monitors the voltage across coupling inductor L2 via voltage feedback lines 42 and 44. In order to provide voltage regulation at the output terminal 58, the firmware product 51 includes instructions for the DSP to vary the form factor, i.e. the phase of the PWM control signal that is applied to the transistor switches 30 25 and 32. In addition to providing regulation, the DSP is also programmed to monitor for, and reject, ripple control signals that may be incoming on output terminal 58, once the inverter is connected to a power grid. 30 The method that the DSP implements, which is programmed as instructions in firmware product 51 will now be explained with reference to the flowchart of Figure 7.

9 At box 60 the inverter current signal that is monitored by transducer 56 is digitised in ADC 50B over a sample window to produce a digitised current signal i(n). Figure 6 depicts a typical cycle of the i(n) signal. It is fundamentally a 50Hz sinusoid but with noise and the ripple signal 5 superimposed. At box 62 the digitised current signal i(n) is processed within DSP 40 to calculate a corresponding RMS current value Ims. At box 64 a sinusoidal 50Hz reference signal iref(n), having an RMS value of Ims is generated. 10 At box 66 idiff(n), being the difference between the actual inverter current i(n) and the calculated reference value iref(n) is calculated. The chart of Figure 9 graphically depicts idiff(n) and it will be observed that it consists of the noise and ripple control signal only. 15 At box 68 idiff(n) is bandpass filtered to remove the noise and produce irippie(n) which represents the ripple control signal incoming on terminal 58 from the grid. The chart of Figure 10 graphically represents irippie(n). 20 At box 70 a 180 degree out of phase signal iati-rippie(n) is calculated by inverting iref(n) as depicted as curve 2 in the graph of Figure 9. At box 72 the inverse ripple signal ianti-ripp 1 e(n) is applied to the PW modulator 38, which in turn controls transistor switches 30, 32 via driver circuits 34, 36. 25 Consequently the current output by the inverter reduces the ripple control current that would otherwise be shunted to ground to almost zero. This reduction has the effect of increasing the impedance of the inverter to ripple control signals. Thus the current due to the ripple current is reduced to close to zero. The inverter presents a high impedance to the incoming ripple signal 30 while maintaining a low impedance to the fundamentals and its harmonics. Referring now to Figure 12, there is depicted a block diagram of an inverter 80 according to a further embodiment of the invention. Inverter 80 includes an 10 Analogue to Digital Converter (ADC) 82 that is coupled to current transducer 56 via preamplifier 76 and anti-aliasing filter 78. The output of the ADC 82 is split in two with a first path being received by RMS generator 84. A sine wave reference generator 86 monitors the output of the RMS current generator and 5 is arranged to produce a sine wave having the predetermined frequency, e.g. 50Hz, and RMS value corresponding to the output from the RMS generator. A difference calculator 88 receives the output from the sine wave reference generator 86 and the second output path from the ADC 82. The output side of the difference calculator 88 is coupled to a bandpass digital filter 90. 10 A frequency analyser module 92 and amplitude analysis module 94 are coupled in parallel to the output of the bandpass digital signal. An inverse sine wave generator 96 is coupled to the output side of the frequency analyser module 92 and the amplitude analysis module 94. Sine wave generator 96 is 15 arranged to generate a control signal with opposite phase to the signal emerging from bandpass digital filter 90. Pulse width modulator 98 takes its control signal from the output of sine wave generator 92. In operation, the inverter 80 is typically coupled to an electrical distribution grid 20 that conveys both mains electrical signals at 50Hz and a ripple control signal whose frequency is not precisely known but which falls within a predetermined frequency range. ADC 82 produces a digital signal i(n) that corresponds to the current through the output of the inverter that is sensed by current transducer 56. RMS current calculator 84 processes i(n) to produce a 25 corresponding RMS value Ims. Sine wave reference generator 86 monitors output from RMS current calculator 84 and in response produces a digital sine wave signal iref(n), of 50Hz frequency and having an RMS value of IRs. Difference calculator 88 subtracts the signal iref(n) from i(n) to produce a difference signal idiff(n) . The difference signal is filtered by digital bandpass 30 filter 90 to remove noise and harmonics thereby producing a digital signal irippie(n), which represents the ripple control signal incident on the output terminal 58 from the distribution grid.

11 The frequency analyser module 92 and amplitude analysis module 94 receive the iripp1e(n) signal and respectively produce signals indicating the frequency and amplitude of the iripp1e(n) signal. The inverse sine wave generator 96 processes the output from the frequency analyser module 92 and amplitude 5 analysis module 94 and generates a signal ianti-rippie(n) having the same amplitude and frequency as irippie(n) but being of opposite phase, i.e. inverted. The ianti-rippie(n) signal is then applied to the PW modulator 98 which in turn produces PWM switching waveforms to drive the transistor switches 30 and 32 via driver circuits 34 and 36. 10 As was also the case with the first-described embodiment of the invention shown in Figure 10, the current output by the inverter reduces the ripple control current that would otherwise be shunted to ground to almost zero. This reduction has the effect of increasing the impedance of the inverter to 15 ripple control signals. Thus the current due to the ripple current is reduced to close to zero. The inverter presents a high impedance to the incoming ripple signal while maintaining a low impedance to the fundamentals and its harmonics. That is, a current sensor is used to extract the current signal from the injected ripple. 20 The PWM signal is then modified to reduce the current caused by the injected ripple towards zero, which has the effect of lifting the impedance of the inverter at the ripple frequency. In compliance with the statute, the invention has been described in language 25 more or less specific to structural or methodical features. The term "comprises" and its variations, such as "comprising" and "comprised of" is used throughout in an inclusive sense and not to the exclusion of any additional features. It is to be understood that the invention is not limited to specific features shown or described since the means herein described 30 comprises preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted by those skilled in the art.

Claims

1. A switch mode device having an output terminal for connection to an electrical network conveying a first signal of predetermined frequency and a second signal of a frequency falling within a predetermined range, the switch mode device being configured to produce a signal at the predetermined frequency at the output terminal and including: a first circuit assembly to detect the second signal; and a second circuit assembly responsive to the first assembly and arranged to operate output switches of the switch mode device to apply a signal in anti-phase to the second signal at the output terminal; wherein the first circuit assembly includes a difference circuit to assist in detecting the second signal.

2. A switch mode device according to claim 1, wherein the first circuit assembly includes a current sensor to produce a signal corresponding to current through the output terminal.

3. A switch mode device according to claim 2, including an analog to digital converter for digitizing said signal of the current sensor.

4. A switch mode device according to claim 3, wherein the first circuit assembly further includes an RMS current calculator coupled to the current sensor, or to the analog to digital converter, to generate a signal indicating an RMS current value for said current sensor signal.

5. A switch mode device according to any one of claims 2 to 4, wherein the first circuit assembly further includes an AC signal reference generator responsive to the RMS current calculator and arranged to produce an AC signal having an RMS value corresponding to the RMS current value.

6. A switch mode device according to claim 5, wherein the difference circuit is responsive to the current sensor and to the AC signal 13 reference generator to generate a difference signal indicating a difference of the AC signal and the current due to the second signal.

7. A switch mode device according to claim 6, wherein the first circuit assembly includes a bandpass filter responsive to the difference circuit to bandpass filter said difference signal over the predetermined range.

8. A switch mode device according to claim 7, wherein the first circuit assembly includes a frequency extraction circuit responsive to the bandpass filter and arranged to produce a frequency signal indicating a frequency of the difference signal.

9. A switch mode device according to claim 7 or claim 8, including an amplitude extraction circuit responsive to the bandpass filter and arranged to produce an amplitude signal indicating an amplitude of the difference signal.

10. A switch mode device according to claim 9, wherein the second circuit assembly further includes a signal inversion circuit to produce an inverted signal corresponding to an inversion of the bandpass filtered signal.

11. A switch mode device according to claim 10, wherein the signal inversion circuit is coupled to respective outputs of the frequency extraction circuit and the amplitude extraction circuit and is arranged to produce the inverted signal based on the amplitude signal and on the frequency signal.

12. A switch mode device according to claim 11, wherein said embodiment the second circuit assembly includes a pulse width modulator controllable by the signal inversion circuit and arranged to generate control signals for controlling said power switches for applying current through the output terminal to prevent attenuation of the ripple control signal. 14

13. A method for operating a switch mode device having an output terminal connectable to a power distribution network to prevent attenuation of a ripple control signal originating in said distribution network, said method comprising the steps of; determining the ripple control signal by digitizing a signal sensed at the output terminal processing the digitized output terminal signal to compute a sinusoidal reference signal corresponding to a power signal component of the signal at the output terminal; and taking the difference of the digitized output terminal signal and the reference signal for determining the ripple control signal; and operating output switches of the switch mode device to apply an anti phase ripple control signal through the terminal to thereby reject said ripple control signal.

14. A switch mode device having an output terminal for connection to an electrical network conveying a first signal of predetermined frequency and a second signal of a frequency falling within a predetermined range, the switch mode device being configured to produce a signal at the predetermined frequency at the output terminal and including: a processor coupled to a current sensor for sensing current through the terminal and arranged to cause switching of output switches coupled to said terminal; and a memory storing a firmware product including instructions for execution by the processor, to determine the second signal by processing a digitized output terminal signal to compute a sinusoidal reference signal corresponding to a power signal component of the signal at the output terminal; and taking the difference of the digitized output terminal signal and the reference signal for determining the ripple control signal; and instructions to cause the processor to operate the output switches to apply an anti-phase version of the second signal to the terminal. 15

15. An inverter for applying power to an electrical power distribution network including a switch mode device according to any one of claims 1 to 12.

16. A switch mode device substantially as described herein with reference to Figure 6.

17. A method of operating a switch mode device substantially as described herein with reference to Figure 7.

18. A firmware product containing instructions for execution by an electronic processor to perform a method substantially as described herein with reference to Figure 7.

19. A switch mode device substantially as described herein with reference to Figure 12.