S&F Ref: 947001 AUSTRALIA PATENTS ACT 1990 COMPLETE SPECIFICATION FOR A STANDARD PATENT Name and Address Canon Kabushiki Kaisha, of 30-2, Shimomaruko 3 of Applicant: chome, Ohta-ku, Tokyo, 146, Japan Actual Inventor(s): Edward James Iskenderian George Politis Oscar Alejandro De Lellis Address for Service: Spruson & Ferguson St Martins Tower Level 35 31 Market Street Sydney NSW 2000 (CCN 3710000177) Invention Title: Edge tracking in scan line batches The following statement is a full description of this invention, including the best method of performing it known to me/us: 5845c(2623956 1) 1 EDGE TRACKING IN SCAN LINE BATCHES FIELD OF THE INVENTION The present invention relates generally to computer-based printer systems and, in particular, to multiprocessor printer systems for high-speed printing. DESCRIPTION OF BACKGROUND ART 5 When a computer application provides data to a device for printing and/or display, a description of the page is often given to device driver software in the form of a page description language (PDL) such Adobe's PDF, which provides descriptions of graphic objects to be rendered onto the page or display. This contrasts with some arrangements where raster image data is generated directly by the application and transmitted for printing or 0 display. For each object described in the page description language, the printer driver is responsible for generating a description of the object that can be understood by the printing device. The rendering system of the printer contains a PDL interpreter that parses a PDL document to produce PDL objects which the printer rendering system uses to build a display list of 15 graphics object data. The rendering system also contains a raster image processor (RIP) that processes the display list and renders the data to a raster image of the page which is made up of pixel values comprising, e.g., C, M, Y and K components. Once in this format, the printer transfers the raster image of the page onto output media such as plain paper. Some raster image processors utilise a pixel-sequential rendering method to remove the 20 need for a frame store, and to overcome the over-painting problem associated with the Painter's algorithm rendering method. In these systems, each pixel in the raster image of the page is generated in raster order. All of the objects to be drawn are retained in a display list. 2621283vl (947001 _Final) 2 Typical pixel rendering apparatuses access data in memory via high speed cache. The high speed cache allows the CPU to have faster access to data that will be reused in the future. Since reading from the cache is much faster than reading from main memory, the high speed cache serves as a major performance booster for CPU instructions that work on localised data. i However the high speed cache is generally a small fraction of the size of the total memory available for the CPU. In some trivial cases, the high speed cache can manage to retain the information without having to re-fetch data from main memory. The high speed cache accesses the data for each edge intersecting the scan line, which is loaded from memory once per scan line. Further, the ) high speed cache sorts and processes the edges loaded from memory on a per scan line basis as well. Both the loading and sorting processes, done on a per scan line basis, result in poor cache utilisation. SUMMARY It is an object of the present invention to substantially overcome, or at least ameliorate, one 5 or more disadvantages of existing arrangements. According to one aspect of the present invention there is provided a method of scan converting a plurality of objects, wherein the plurality of objects are present for a strip comprising a plurality of scan lines of an output image, said method comprising the steps of, for said strip in said output image: 20 tracking an edge for in the strip; storing said tracked edge position into a buffer; progressing to a next edge once the edge has been tracked in the strip; and for each scan line of the strip, using the stored edge position to determine an active edge and at least one pixel span. 2621283vl (947001_Final) 3 According to another aspect of the present invention there is provided a method for generating a stroke outline for a path subject to a geometric transformation, said method comprising the steps of: transforming the path from a first coordinate system to a second coordinate system; 5 determining if the transformation scales uniformly in all directions; and if so, generating the stroke outline from the transformed path, wherein said generation is performed substantially within the second coordinate system. Other aspects of the invention are also disclosed. BRIEF DESCRIPTION OF THE DRAWINGS 0 One or more embodiments of the invention will now be described with reference to the following drawings, in which: Figs. I a to I c collectively form a schematic block diagram of a pixel rendering system, upon which arrangements described can be practiced; Fig. 2 is a schematic block diagram of a method of creating an intermediate format of a L5 page; Fig. 3 is a schematic block diagram of a method of performing object tracking; Fig. 4 is an example of an edge structure used to track an edge over multiple scan lines. Fig. 5a is an example of PDL objects on a page which intersect a strip of scan lines; Fig. 5b is an example of PDL objects on a page which intersect a strip of scan lines, and 20 the edges to be tracked for duration of strip; Fig. 5c is an example of PDL objects on a page which intersect a strip of scan lines, and the edges that have been tracked and pixel aligned for duration of strip; Fig. 5d is an example of PDL objects on a page which intersect a strip of scan lines, and the spans generated by scan line edge crossing on a scan line within the strip; 25 Fig 6a shows an example of a line-art path specified in a first co-ordinate space; 2621283v1 (947001_Final) 4 Fig 6b shows an example of result of stroking the line-art sub-path of Fig. 1A and displaying it in a second co-ordinate space; and Fig 7 is a flow diagram showing a method of stroking line-art paths. DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION 5 Where reference is made in any one or more of the accompanying drawings to steps and/or features, which have the same reference numerals, those steps and/or features have for the purposes of this description the same function(s) or operation(s), unless the contrary intention appears. During the rendering of the display list to a raster image, at each scan line the edges of each 0 of the objects which intersect that scan line are held in increasing order of intersection with the scan line in an active edge list. These points of intersection, or edge crossings, are considered in turn, and are used to activate or deactivate objects in the display list. Between each pair of edges considered, the colour data for each pixel which lies between the first edge and the second edge is generated based on which objects are not obscured by opaque objects 5 for that span of pixels (pixel-run). When the end of a scan line has been reached, the coordinate of intersection of each edge with the next scan line is updated in accordance with the nature of the edge in preparation for the next scan line. These edges then are sorted in increasing order of intersection with the next scan line. Any new edges are also merged into the active edge list. Furthermore, any 20 edges which are no longer active are removed from the active edge list. A specific application of pixel-sequential rendering involves a first stage in which edges are tracked, without generating colour data. Rather, a plurality of non-overlapping regions are formed, and each region is assigned a unique set of fills which will be used to determine the colour of pixels in the region in subsequent rendering stage. The description of the unique 25 regions is stored in a region-based representation. The region-based representation is then 2621283v1 (947001 _Final) 5 passed to a renderer, which generates pixel data for each region to form a raster image representation of the page. The renderer generates pixel data for each scan line by determining which regions intersect that scan line and generating pixel data for these regions using the corresponding fill data. 5 Figs. I a to I c collectively form a schematic block diagram of a pixel rendering system 100, upon which the various arrangements described can be practiced. As seen in Fig. I a, the system 100 is formed by a computer module 101, input devices such as a keyboard 102, a mouse pointer device 103, a scanner 126, a camera 127, and a microphone 180, and output devices including a printer 15, a display device 114 and 0 loudspeakers 117. An external Modulator-Demodulator (Modem) transceiver device 116 may be used by the computer module 101 for communicating to and from a communications network 120 via a connection 121. The network 120 may be a wide-area network (WAN), such as the Internet or a private WAN. Where the connection 121 is a telephone line, the modem 116 may be a traditional "dial-up" modem. Alternatively, where the connection 121 .5 is a high capacity (e.g., cable) connection, the modem 116 may be a broadband modem. A wireless modem may also be used for wireless connection to the network 120. The computer module 101 typically includes at least one processor unit 105, and a memory unit 106 for example formed from semiconductor random access memory (RAM) and semiconductor read only memory (ROM). The module 101 also includes a number of 20 input/output (I/O) interfaces including an audio-video interface 107 that couples to the video display 114, loudspeakers 117 and microphone 199, an I/O interface 113 for the keyboard 102, mouse 103, scanner 126, camera 127 and optionally a joystick (not illustrated), and an interface 108 for the external modem 116. In some implementations, the modem 116 may be incorporated within the computer module 101, for example within the interface 108. 25 The computer module 101 also has a local network interface 111 which, via a connection 123, 2621283vl (947001_Final) 6 permits coupling of the pixel rendering system 100 to a local computer network 122, known as a Local Area Network (LAN). As also illustrated, the local network 122 may also couple to the wide network 120 via a connection 124, which would typically include a so-called "firewall" device or device of similar functionality. The interface Ill may be formed by an 5 Ethernetm circuit card, a Bluetooths wireless arrangement or an IEEE 802.11 wireless arrangement. The interfaces 108 and 113 may afford either or both of serial and parallel connectivity, the former typically being implemented according to the Universal Serial Bus (USB) standards and having corresponding USB connectors (not illustrated). Storage devices 109 are provided 0 and typically include a hard disk drive (HDD) 110. Other storage devices such as a floppy disk drive and a magnetic tape drive (not illustrated) may also be used. An optical disk drive 112 is typically provided to act as a non-volatile source of data. Portable memory devices, such optical disks (e.g., CD-ROM, DVD), USB-RAM, and floppy disks for example may then be used as appropriate sources of data to the system 100. .5 The components 105 to 113 of the computer module 101 typically communicate via an interconnected bus 104. Examples of computers on which the described arrangements can be practised include IBM-PC's and compatibles, Sun Sparcstations, Apple Mac" or alike computer systems evolved therefrom. Methods described below may be implemented using the system 100 wherein the processes 20 of Figs. 2 to 14, to be described, may be implemented as one or more software application programs 133 and/or the controlling program 176 (see Fig. I c) executable within the system 100. In particular, the steps of the described methods are effected by instructions 131 in the software that are carried out within the system 100. The software instructions 131 may be formed as one or more software code modules, each for performing one or more particular 25 tasks. The software may also be divided into two separate parts, in which a first part and the 2621283vl (947001 Final) 7 corresponding software code modules performs the described methods and a second part and the corresponding software code modules manages user interface between the first part and the user. The software may be stored in a computer readable medium, including the storage devices 5 described below, for example. The software is loaded into the system 100 from the computer readable medium, and then executed by the system 100. A computer readable medium having such software or computer program recorded on it is a computer program product. The use of the computer program product in the system 100 preferably effects an advantageous apparatus for implementing the described methods. 0 The software 133 is typically stored in the HDD 110 or the memory 106. The software 133 is loaded into the system 100 from a computer readable medium, and then executed by the system 100. Thus for example the software may be stored on an optically readable CD-ROM medium 125 that is read by the optical disk drive 112. A computer readable medium having such software or computer program recorded on it is a computer program product. The use of 5 the computer program product in the computer system 100 preferably effects an advantageous apparatus for implementing the described methods. In some instances, the application programs 133 may be supplied to the user encoded on one or more CD-ROM 125 and read via the corresponding drive 112, or alternatively may be read by the user from the networks 120 or 122. Still further, the software can also be loaded 20 into the system 100 from other computer readable media. Computer readable storage media refers to any storage medium that participates in providing instructions and/or data to the system 100 for execution and/or processing. Examples of such storage media include floppy disks, magnetic tape, CD-ROM, a hard disk drive, a ROM or integrated circuit, USB memory, a magneto-optical disk, or a computer readable card such as a PCMCIA card and the like, 25 whether or not such devices are internal or external of the computer module 101. Examples of 2621283vl (947001_Final) 8 computer readable transmission media that may also participate in the provision of software, application programs, instructions and/or data to the computer module 101 include radio or infra-red transmission channels as well as a network connection to another computer or networked device, and the Internet or Intranets including e-mail transmissions and information 5 recorded on Websites and the like. The second part of the application programs 133 and the corresponding code modules mentioned above may be executed to implement one or more graphical user interfaces (GUls) to be rendered or otherwise represented upon the display 114. Through manipulation of typically the keyboard 102 and the mouse 103, a user of the system 100 and the application 0 may manipulate the interface in a functionally adaptable manner to provide controlling commands and/or input to the applications associated with the GUI(s). Other forms of functionally adaptable user interfaces may also be implemented, such as an audio interface utilizing speech prompts output via the loudspeakers 117 and user voice commands input via the microphone 180. 5 Fig. lb is a detailed schematic block diagram of the processor 105 and a "memory" 134. The memory 134 represents a logical aggregation of all the memory modules (including the HDD 109 and semiconductor memory 106) that can be accessed by the computer module 101 in Fig. la. When the computer module 101 is initially powered up, a power-on self-test (POST) 20 program 150 executes. The POST program 150 is typically stored in a ROM 149 of the semiconductor memory 106. A hardware device such as the ROM 149 is sometimes referred to as firmware. The POST program 150 examines hardware within the computer module 101 to ensure proper functioning, and typically checks the processor 105, the memory (109, 106), and a basic input-output systems software (BIOS) module 151, also typically stored in the 25 ROM 149, for correct operation. Once the POST program 150 has run successfully, the 2621283v (947001_Final) 9 BIOS 151 activates the hard disk drive 110. Activation of the hard disk drive 110 causes a bootstrap loader program 152 that is resident on the hard disk drive 110 to execute via the processor 105. This loads an operating system 153 into the RAM memory 106 upon which the operating system 153 commences operation. The operating system 153 is a system level 5 application, executable by the processor 105, to fulfil various high level functions, including processor management, memory management, device management, storage management, software application interface, and generic user interface. The operating system 153 manages the memory (109, 106) in order to ensure that each process or application running on the computer module 101 has sufficient memory in which to 0 execute without colliding with memory allocated to another process. Furthermore, the different types of memory available in the system 100 must be used properly so that each process can run effectively. Accordingly, the aggregated memory 134 is not intended to illustrate how particular segments of memory are allocated (unless otherwise stated), but rather to provide a general view of the memory accessible by the system 100 and how such is 15 used. The processor 105 includes a number of functional modules including a control unit 139, an arithmetic logic unit (ALU) 140, and a local or internal memory 148, sometimes called a cache memory. The cache memory 148 typically includes a number of storage registers 144 146 in a register section. One or more internal busses 141 functionally interconnect these 20 functional modules. The processor 105 typically also has one or more interfaces 142 for communicating with external devices via the system bus 104, using a connection 118. The application program 133 includes a sequence of instructions 131 that may include conditional branch and loop instructions. The program 133 may also include data 132 which is used in execution of the program 133. The instructions 131 and the data 132 are stored in 25 memory locations 128-130 and 135-137 respectively. Depending upon the relative size of the 2621283vl (947001_Final) 10 instructions 131 and the memory locations 128-130, a particular instruction may be stored in a single memory location as depicted by the instruction shown in the memory location 130. Alternately, an instruction may be segmented into a number of parts each of which is stored in a separate memory location, as depicted by the instruction segments shown in the memory 5 locations 128-129. In general, the processor 105 is given a set of instructions which are executed therein. The processor 105 then waits for a subsequent input, to which the processor 105 reacts to by executing another set of instructions. Each input may be provided from one or more of a number of sources, including data generated by one or more of the input devices 102, 103, 0 data received from an external source across one of the networks 120, 102, data retrieved from one of the storage devices 106, 109 or data retrieved from a storage medium 125 inserted into the corresponding reader 112. The execution of a set of the instructions may in some cases result in output of data. Execution may also involve storing data or variables to the memory 134. [5 The described methods use input variables 154 that are stored in the memory 134 in corresponding memory locations 155-158. The described methods produce output variables 161 that are stored in the memory 134 in corresponding memory locations 162-165. Intermediate variables may be stored in memory locations 159, 160, 166 and 167. The register section 144-146, the arithmetic logic unit (ALU) 140, and the control unit 139 20 of the processor 105 work together to perform sequences of micro-operations needed to perform "fetch, decode, and execute" cycles for every instruction in the instruction set making up the program 133. Each fetch, decode, and execute cycle comprises: (a) a fetch operation, which fetches or reads an instruction 131 from a memory location 128; 2621283v1 (947001 _Final) 11 (b) a decode operation in which the control unit 139 determines which instruction has been fetched; and (c) an execute operation in which the control unit 139 and/or the ALU 140 execute the instruction. 5 Thereafter, a further fetch, decode, and execute cycle for the next instruction may be executed. Similarly, a store cycle may be performed by which the control unit 139 stores or writes a value to a memory location 132. Each step or sub-process in the processes of Figs. 4 to 6 is associated with one or more segments of the program 133, and is performed by the register section 144-147, the ALU 140, 0 and the control unit 139 in the processor 105 working together to perform the fetch, decode, and execute cycles for every instruction in the instruction set for the noted segments of the program 133. The described methods may alternatively be implemented in dedicated hardware such as one or more integrated circuits performing the functions or sub functions of the methods. 5 Such dedicated hardware may include graphic processors, digital signal processors, or one or more microprocessors and associated memories. Fig. Ic shows the computer module 101 connected to the printer 115 via the network 122.As described above, the network 122 may be a local computer network 122, known as a Local Area Network (LAN) with multiple personal computers connected to the network 122. 20 Alternatively, the network 122 may be a simple connection between the computer 101 and the printer 115. The printer 115 comprises a controller processor 169 for executing a controlling program 176, a pixel rendering apparatus 195, a high speed cache 180, and a printer engine 190 coupled via a bus 185. The high speed cache 180 is coupled to memory 170 via a bus 175. 25 The pixel rendering apparatus 195 can be in the form of an ASIC coupled via the bus 185 to 2621283v (947001 _Final) 12 the controller processor 169, and the printer engine 190. However, the pixel rendering apparatus 195 may also be implemented in software executed in the controller processor 169. In the pixel rendering system 100, the software application 133 creates page-based documents where each page contains objects such as text, lines, fill regions, and image data. 5 The software application 133 sends a high-level description of the page, such as a PDL file, via the network 122 to the controlling program 176 executing in the controller processor 169 of the printer 115. The controlling program 176 then interprets the high-level description of the page to form rendering instructions which are sent to the pixel rendering apparatus 195. The program 176 executing on the controller processor 169 is also responsible for providing 0 memory 170 for the pixel rendering apparatus 195, initialising the pixel rendering apparatus 195, and instructing the pixel rendering apparatus 195 to start rendering the page. The pixel rendering apparatus 195 then uses the rendering instructions to render the page to pixels. The output of the pixel rendering apparatus 195 is colour pixel data, which may be used by the printer engine 190. 5 When the controlling program 165 receives the description of the page from the software application 133 the controlling program 176 first converts objects in the page description into an intermediate page representation called a display list. Each object in the display list generally contains a priority, edges and fill data. A fill for an object indicates to the pixel rendering apparatus 195 how to generate colour information for pixels contained between 20 edges of the object. Examples of the types of fills that may be used are flat colours, bitmaps, linear blends and radial blends. The controlling program 176 will convert the object specified in the page description into a fill instruction that can be used by the pixel rendering apparatus 195 to generate pixel colour data. Each fill instruction is executed for each pixel in which the corresponding object is active. 25 The controlling program 169 determines the region of pixels for which each object is active. 2621283vl (947001_Final) 13 Due to the complex nature of PDL graphics, the controlling program 169 is configured for efficiently determining the regions of pixels in which each object is active, and then generating a set of instructions which are efficient for the pixel rendering apparatus 195 to perform. 5 Fig 2 shows the method used by the controlling program 176 to generate fill instructions for a page described by a PDL file. The method 200 may be used for scan-converting a plurality of objects of such a page. The method 200 begins with entry into the page interpretation step 210 where the objects in the PDL file are converted into a display list. The display list is then processed in the object tracking step 220, where the region activated by 0 each element in the display list is calculated to the correct pixel, at a given pixel resolution. In order to avoid caching shortcomings of pixel-sequential rendering, object tracking is performed in two stages. During the first stage each edge is loaded into the high speed cache 180 from memory 170 in turn. While an edge is stored in the cache, the edge is tracked for a number of scan lines n with each scan line position of the edge saved in a buffer. The number 5 of scan lines is predetermined and is dependent on the properties of the high-speed cache 180. During the second stage, the tracking data determined for each edge is used to sort the edges and determine the objects which are active in each span, for each scan line in the n scan line strip. Fig. 4 shows a simplified layout of an edge structure 400 used to represent an each object 20 edge. The edge structure 400 comprises the main edge data 410, a current position 420 and a position buffer 430. The position buffer should be sized to maximize high speed cache 180 efficiency, together with the overall efficiency of the controlling program 176. Fig. 3 shows a method 220 of performing object tracking, as executed in step 220. In Fig. 3, a strip refers to an area to be rendered that spans the entire width of the page, which is 25 made up of a plurality of contiguous scan lines, of the page. The method 220 starts with a 2621283vl (947001 _Final) 14 strip load step 310, where a strip of a page is prepared by determining which PDL objects intersect the strip, and further determining which if any of these PDL objects start or end in the strip. The sequence then proceeds to the edge load step 315, where one edge of an object is loaded into cache. While keeping the edge in the cache, the edge update step 320 is 5 preformed. The edge update step 320 consists of using the geometric properties of an edge to determine the position on the current scan line. The method 220 then proceeds to the edge strip complete decision step 325 which returns to the edge update 320 step and proceeds to the next scanline if the strip is not complete. Otherwise, the method 220 of Fig. 3 proceeds to the tracking all edges decision complete step 0 330. In the tracking all edges complete decision step 330, if all edges are not completed for the strip, then the sequence resets the scan line count to the start of the strip and returns to edge load 315 step for progressing to a next edge. At step 315, the next edge is loaded. Otherwise, if tracking all edges complete decision step 330 returns in the affirmative, then the method proceeds to the sort edge step 335. During the sort edges step 335, the edges on the 5 current scan line are sorted based on their pixel position of the current scan line which is stored in position buffers for each edge in the strip. After the sort edges step 335 completes for a scan line, the method proceeds to the generate spans step 340. In the generate spans step 340 each span is determined based on each of the edge intersections for the current scan line, and pixel colour and attribute data is generated. Next the sequence moves to the sorting strip 20 complete decision step 345. If the complete strip has been sorted, the sequence moves to the page complete decision step 350, otherwise the sequence returns to sort edge 335 step and the next scan line is processed. In the page complete decision step 350, if the page has been completely processed the method 220 returns to step the construct fill instructions step 240 in Fig. 2, otherwise the method 220 returns to strip load step 310. Alternatively, in the generate 2621283vl (947001_Final) 15 span step 340, each determined span can be used to generate an intermediate page representation that can later be rendered to pixel colour and attribute data. Using the method 220 of Fig 3, the update edge step 320 will keep an edge in high speed cache 180 for the duration of the strip. The method 220 given may reduce cache misses during 5 edge update step 320 by a factor of a, where a is the number of scan line lines in the strip, because the edge will only need to be loaded into high speed cache 180 once per a scan lines as opposed to once per scan line. However, there are limitations to the size of a which provide gains over prior art due to high speed cache 180 properties and subsequent steps being performed during edge sorting and span processing. 0 The methods described above will now be described in further detail by way of example with reference to Figs. 5a to 5d. Fig 5a show an example of PDL objects 520 - 524 on a page 500. Strip 510 contains a predetermined number of scan lines for which the strip 510 intersects PDL objects 520 - 524. In Fig. 5b, PDL objects 520 - 524 on a page 500 that are present in strip 510 have their edges .5 identified for tracking and sorting. The identified edges are each tracked for the duration of the strip in a serial manner to ensure that each edge remains in high-speed cache 180 recording each position in the edge position buffer 430. The result of tracking the edges are pixel-accurate edge representations 540 - 549 shown in Fig 5c. For example, the method will take edge 530 and track the edge 530 for the duration of strip 510 storing positions in edge 20 position buffer 430 before tracking any other edge. Fig 5d shows a single scan line 505 after all edges have been tracked for a strip. The scan line 505 is now composed of spans 540 - 551 which were determined from sorted edges 530 - 539. Returning now to Fig. 2, after the track objects step 220 is complete, the construct fill instruction step 230 is performed. The construct fill instruction step 230 creates a group of fill 2621283vl (947001_Final) 16 instructions into a page representation that can be rendered by pixel rendering apparatus 195 at some point. Rendering, which converts a PDL (e.g. Adobe@ PostScript@, or Hewlett-Packard@ PCL) commonly takes place in a device-specific geometric coordinate space (or coordinate space). 5 Line-art specified in PDL files typically has paths and attributes that specify the appearance of the rendered output to the imaging device. A process often referred to as "stroking" applies the line-art attributes to the line-art paths to produce an intermediate representation that can then be rendered by the imaging device. As described, the paths may be subject to a geometric transformation. Line-art attributes may comprise a line width, a dash patterns, and 0 types of caps and joins. In one embodiment of the stroking process, the line-art attributes are applied to a path to produce points for generating an outline of the intermediate representation. The points form the outline of the intermediate representation. The line-art attributes and paths are commonly defined in a first co-ordinate space (or co-ordinate system) which differs from the co-ordinate .5 space (or co-ordinate system) in which rendering takes place. One common method of stroking is to traverse the points in all the line-art sub-paths in the line-art path to generate points on either side of them which are conforming to the line width attribute. Additional points are generated to produce caps, joins and dashes. Generated points are then converted to the rendering co-ordinate space before being rendered by the imaging 20 device. Accordingly, the generation of the points is performed substantially within a particular co-ordinate space (or co-ordinate system) before being converted to the rendering co-ordinate space (or co-ordinate system). The stroking method makes use of potentially large amounts of memory and does not benefit from the spatial properties of the line-art sub paths within the line-art paths. 2621283vl (947001_Final) 17 Another method of stroking is to traverse the points in the path with a brush of particular geometric properties that will produce an intermediate representation conforming to the line art attributes specified in the PDL file. The chosen brush limits the amount of artistic freedom that the artist creating the PDL file enjoys. 5 In one embodiment, a line-art path to stroke is received. Fig 6a shows a line-art path composed of sub-paths 600 and 601 in a first co-ordinate space (or co-ordinate system) 602. Fig. 6b shows lines 603 and 604 being the end result of stroking the line-art sub-paths 600 and 601 respectively in a second co-ordinate space (or co-ordinate system) 605. The conversion of the line-art shown in Fig l a to the stroked lines shown in Fig lb will now be 0 described in detail. A method 700 of stroking line-art paths will now be described in detail below with reference to Fig 7. At first storing step 701, all of the PDL line-art objects are first transformed to render-co-coordinate space. At sorting step 702, the PDL line-art objects are then sorted into an appropriate data-structure, which permits objects starting at a particular 5 scan line to be added and iterated through. Beginning at traversing step 703, in the method 700, all the objects are traversed in each render-space scan line, starting at the least scan line in which an object occurs. The following decision step 707 determines whether or not the current object is a line-art sub-path. At breaking step 704, an object that is not a line-art sub path (i.e., is still an entire line-art path) is broken into sub-paths. Each resulting sub-path is 20 then added back into the data-structure created at sorting step 702 at re-posting step 715. The method 700 then proceeds to decision step 712 to continue looping over the objects starting at the current scan line. However, if the object seen at decision step 707 was a sub-path, then properties of the objects, in particular the transformation matrix from user-space to render-space are examined 2621283vl (947001_Final) 18 at determining step 714 to determine whether the sub-path can be stroked in its current co ordinate space, that being in render-space, or require extra processing. The determining step 714 involves determining whether the user-space to render-space transformation matrix scales a line of given length uniformly in all directions regardless of its 5 orientation. This means that scaling is uniform (the same in both x and y) and that there is no shearing. The determination may be made at step 714 by comparing coefficients of the transformation matrix. In particular, given a matrix [ representing the non-translation Ic d components of the user-space to render-space transformation matrix of the line-art path, stroking may be performed in render space if either of the following conditions hold true 0 (b + c)= (a - d) 0, or (b - c)= (a + d)= 0. If, at the determining step 714, it is determined that the line-art sub-path cannot be stroked in user-space then the line-art sub-path has an inverted transformation matrix applied to return the sub-path to user-space at step 706, before being stroked at step 708. After stroking, the 5 line-art sub-path is converted back to user-space at step 709 before being output at step 710. However, should the determining step 714 determine that the line-art sub-path can be stroked in render-space then the line-art sub-path is stroked at step 716 before being output at step 710. The method 700 then proceeds to decision step 712 to continue looping over the objects starting at the current scan line. 20 The steps of the method 700 described above are repeated for all line-art sub-paths at a particular scan line. Thereafter, the method 700 proceeds to decision step 713 where the method 700 is applied to the objects in remaining scan lines. The described methods provide peak-memory savings and speed improvements in the case of stroking in render-space. Whereas prior art will stroke all line-art sub-paths of the line-art 2621283vl (947001_Final) 19 paths in a PDL up front, the described methods stroke each line-art sub-path when the scan line at which the sub-path begins is reached. The described methods result in peak memory reductions. Likewise, prior art performing stroking in user space will have to transform a greater number of stroke outline point co-ordinates from user space into render space than the i described methods, which creates stroke outline points from render-space line-art sub-path points, thereby providing a performance improvement. On occasion it is required to transform line-art sub-paths back into user space for stroking and again to render space for rendering. However, experience shows that this happens only in a small minority of cases. Industrial Applicability ) The arrangements described are applicable to the computer and data processing industries and particularly for the scan-converting and stroke outline generation. The foregoing describes only some embodiments of the present invention, and modifications and/or changes can be made thereto without departing from the scope and spirit of the invention, the embodiments being illustrative and not restrictive. 5 In the context of this specification, the word "comprising" means "including principally but not necessarily solely" or "having" or "including", and not "consisting only of'. Variations of the word "comprising", such as "comprise" and "comprises" have correspondingly varied meanings. 20 2621283v l (947001l_Final)