AU2009200888A1 - Electrical connection of a substrate within a vacuum device via electrically conductive epoxy/paste - Google Patents

Electrical connection of a substrate within a vacuum device via electrically conductive epoxy/paste Download PDF

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Publication number
AU2009200888A1
AU2009200888A1 AU2009200888A AU2009200888A AU2009200888A1 AU 2009200888 A1 AU2009200888 A1 AU 2009200888A1 AU 2009200888 A AU2009200888 A AU 2009200888A AU 2009200888 A AU2009200888 A AU 2009200888A AU 2009200888 A1 AU2009200888 A1 AU 2009200888A1
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Prior art keywords
ceramic substrate
imager
input
image intensifier
output
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AU2009200888A
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Benjamin Brown
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ITT Manufacturing Enterprises LLC
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ITT Manufacturing Enterprises LLC
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J31/00—Cathode ray tubes; Electron beam tubes
    • H01J31/08—Cathode ray tubes; Electron beam tubes having a screen on or from which an image or pattern is formed, picked up, converted, or stored
    • H01J31/50—Image-conversion or image-amplification tubes, i.e. having optical, X-ray, or analogous input, and optical output
    • H01J31/506—Image-conversion or image-amplification tubes, i.e. having optical, X-ray, or analogous input, and optical output tubes using secondary emission effect
    • H01J31/507—Image-conversion or image-amplification tubes, i.e. having optical, X-ray, or analogous input, and optical output tubes using secondary emission effect using a large number of channels, e.g. microchannel plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J43/00—Secondary-emission tubes; Electron-multiplier tubes
    • H01J43/04—Electron multipliers
    • H01J43/06—Electrode arrangements
    • H01J43/18—Electrode arrangements using essentially more than one dynode
    • H01J43/24—Dynodes having potential gradient along their surfaces
    • H01J43/246—Microchannel plates [MCP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2231/00—Cathode ray tubes or electron beam tubes
    • H01J2231/50—Imaging and conversion tubes
    • H01J2231/50057—Imaging and conversion tubes characterised by form of output stage
    • H01J2231/50068—Electrical
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Description

AUSTRALIA Patents Act 1990 COMPLETE SPECIFICATION Standard Patent Applicant (s): ITT MANUFACTURING ENTERPRISES, INC. Invention Title: ELECTRICAL CONNECTION OF A SUBSTRATE WITHIN A VACUUM DEVICE VIA ELECTRICALLY CONDUCTIVE EPOXY/PASTE The following statement is a full description of this invention, including the best method for performing it known to me/us: -1A ELECTRICAL CONNECTION OF A SUBSTRATE WITHIN A VACUUM DEVICE VIA ELECTRICALLY CONDUCTIVE EPOXY/PASTE FIELD OF THE INVENTION The present invention relates, in general, to vacuum devices, such as image intensifier tubes. More specifically, the present invention relates to an electron gain device, such as a microchannel plate (MCP), configured for close 5 contact to an electron sensing device, such as a CMOS imager. BACKGROUND OF THE INVENTION Image intensifying devices may use solid state sensors, such as CMOS or CCD devices. Image intensifier devices amplify low intensity light or convert non visible light into regularly viewable images. Image intensifier devices have many 10 industrial and military applications. For example, image intensifier tubes may be used for enhancing the night vision of aviators, photographing astronomical events and providing night vision to sufferers of night blindness. There are three types of image intensifying devices: image intensifier tubes for cameras, solid state CMOS (complementary metal oxide semiconductor) is and CCD (charge coupled device) sensors, and hybrid EBCCD/CMOS (electronic bombarded CCD or CMOS) sensors.
-2 Referring to FIG. 1, there is shown a schematic diagram of an image intensifier tube, generally designated as 10. As shown, light energy 14 reflected from object 12 impinges upon photocathode 16. Photocathode 16 receives the incident energy on input surface 16a and outputs the energy, as emitted electrons, 5 on output surface 16b. The output electrons, designated as 20, from photocathode 16, are provided as an input to an electron gain device, such as MCP 18. The MCP includes input surface 18a and output surface 18b. As electrons bombard input surface 18a, secondary electrons are generated within micro-channels 22 of MCP 18. The MCP generates several hundred electrons for each electron entering input surface 10 18a. Although not shown, it will be understood that MCP 18 is subjected to a difference in voltage potential between input surface 18a and output surface 18b, typically over a thousand volts. This potential difference enables electron multiplication. Electrons 24 are outputted from MCP 18 and impinge upon solid state 15 electron sensing device 26. Electron sensing device 26 may be a CMOS imager, for example, and includes input surface 26a and output surface 26b, as shown in FIG. 1. Electron sensing device 26 may be fabricated as an integrated circuit, using CMOS processes. In general, the CMOS imager employs electron sensing elements. 20 Input surface 26a includes an active receive area sensitive to the received electrons from MCP 18. The output signals of the electron sensing elements may be provided, at output surface 26b (actually an output surface of a ceramic header), as signals whose magnitudes are proportional to the amount of electrons received by the electron sensing elements. The number of electrons is proportional to incoming 25 photons at the cathode. CMOS imagers use less power and have lower fabrication cost compared to imagers made by CCD processes.
- 3 The output of CMOS imager 26 produces an intensified image signal that may be sent, by way of a bus, to image display device 28. The output of CMOS imager 26 may be, alternatively, stored in a memory device (not shown). To facilitate the multiplication of electrons between the input of the s image intensifier tube, at input surface 16a, and the output of the image intensifier tube, at output surface 26b, a vacuum housing is provided. As shown, photocathode 16, MCP 18 (or other electron gain device) and CMOS imager 26 (or other electron sensing device) are packaged in vacuum housing 29. In addition to providing a vacuum housing, input surface 26a of the CMOS imager and output surface 18b of 1o the MCP are required to physically be very closely spaced from each other. Such close spacing presents a problem, because a conventional silicon die of a CMOS imager, for example, includes wires looping above the input surface of the imager for outputting the intensified image signal. Because these wires flare out from the silicon die and loop above the input surface, before they are connected to 15 bond pads on a ceramic carrier holding the silicon die, it is difficult to closely space the input surface of the imager to the output surface of the MCP. As an example, a conventional silicon die is shown in FIGS. 2a and 2b. As shown, chip 30 includes silicon die 32 attached to ceramic carrier 34 (also referred to herein as header 34). The silicon die includes an array of terminal pads 36 for 20 providing input/output (I/O) signals. Hundreds of terminal pads 36 are typically disposed around the peripheral circumference of silicon die 32. Also shown in FIGS. 2a and 2b is an array of pads 38 disposed on ceramic carrier 34. Leads or wires 40 are attached by ultrasonic bonding of wires between I/O pads 36 and I/O pads 38, thereby making electrical contact between them. Extending from the bottom of 25 ceramic carrier 34 are a plurality of pins 42, as shown in FIG. 2b, which are connected through via-holes (for example, 39a and 39b) to the array of bond pads -4 38. In this manner, electrical contacts are made between bond pads 36 on silicon die 32 and the input/output of the chip, at the plurality of pins 42. In a typical conventional configuration, wires 40 loop above the planar top surface of silicon die 32 and then descend down toward ceramic carrier 34, as 5 shown in FIG. 2b. These wire loops above silicon die 32, in the case of a conventional CMOS imager (for example), prevent a tight vertical placement between the top active surface area of silicon die 32 and the output surface area of electron gain device 18. As best shown in FIG. 2c, output surface 18b of electron gain device 18 is placed in close vertical proximity to the input surface area of silicon die 32. 10 Because of the looping of wires 40, however, it is not possible to reduce the vertical space between output surface 18b and the top surface of silicon die 32. The lowest wire bond profile is limited to the wire bond height plus a vertical clearance to assure the wires do not contact the silicon surface and become shorted. The vertical clearance is also limited to the bondwire loop height plus a distance required to 15 provide a voltage standoff between the output surface of the electron gain device and the input surface of the electron sensing device. As will be explained, the present invention addresses this shortcoming by providing an electron sensing device with a pocket, which may receive an electron sensing device and permit a tight interface, or small clearance between the electron 20 sensing device and the electron gain device (for example, an MCP). SUMMARY OF THE INVENTION To meet this and other needs, and in view of its purposes, the present invention provides an image intensifier including a microchannel plate (MCP) having an output surface, and a ceramic substrate having an outer surface. The output 25 surface of the MCP and the outer surface of the ceramic substrate are oriented facing - 5 each other. An imager is substantially buried within the ceramic substrate, and an input surface of the imager is exposed to receive light from the output surface of the MCP. The input surface of the imager and the outer surface of the ceramic 5 substrate are oriented in substantially the same plane. The input surface of the imager and the outer surface of the ceramic substrate are disposed at a distance from the output surface of the MCP that is less than or equal to 0.005 inches. The imager includes input/output pads, and the ceramic substrate includes other input/output pads. A conductive epoxy connects a respective 1o input/output pad of the imager to a respective input/output pad of the ceramic substrate. Multiple conductive epoxies may connect multiple input/output pads of the imager to multiple input/output pads of the ceramic substrate. The imager may include a CMOS (complementary metal oxide semiconductor) device, or a CCD (charge coupled device). 15 The ceramic substrate includes a pocket having a seat at a predetermined depth. The imager is configured to be received in the pocket, with a bottom surface of the imager disposed directly on top of the seat. The top surface of the ceramic substrate and the input surface of the imager are substantially coplanar. A conductive epoxy spans between (a) input/output pads disposed on the input 20 surface of the imager and (b) input/output pads disposed on the top surface of the ceramic substrate for electrically connecting the imager to the ceramic substrate. A non-conductive epoxy may be deposited in the pocket. The non-conductive epoxy is configured to fill gaps between (a) end surfaces of the imager inserted in the pocket and (b) walls of the pocket. 25 Another embodiment of the present invention includes an image intensifier including an electron gain device having an output surface; and an -6 electron sensing device having an input surface, positioned below the output surface of the electron gain device, for receiving light from the output surface of the electron gain device. A ceramic substrate is disposed below the output surface of the electron gain device for housing the electron sensing device. A top surface of the ceramic 5 substrate is substantially coplanar with the input surface of the electron sensing device. The ceramic substrate includes a pocket for housing the electron sensing device. The pocket is of a predetermined depth so that the top surface of the ceramic substrate is substantially coplanar with the input surface of the electron sensing device. Input/output pads are disposed on the top surface of the ceramic io substrate. Input/output pads are disposed on the input surface of the electron sensing device. Multiple conductive epoxy spans are included for electrically connecting the input/output pads of the ceramic substrate and the electron sensing device. Non-conductive epoxy is disposed below at least one conductive epoxy span for providing support to the at least one conductive epoxy span. is Yet another embodiment of the present invention is a method of making an image intensifier. The method includes the steps of: forming a pocket in a ceramic substrate; housing an imager in the pocket of the ceramic substrate; and spanning conductive epoxy between input/output pads of the ceramic substrate and the imager. 20 The step of forming a pocket includes forming a seat in the pocket at a predetermined depth; and the step of housing includes placing the ceramic substrate on top of the seat in the pocket, so that the top surface of the imager is coplanar with the top surface of the ceramic substrate. The method of making an image intensifier may include the step of: 25 inserting a non-conductive epoxy in gaps formed between edges of the ceramic substrate and edges of the imager. Furthermore, the step of spanning includes -7 spanning the conductive epoxy in a horizontal direction across the gaps that have been filled with the non-conductive epoxy. After housing the imager in the pocket of the ceramic substrate, an output surface of an MCP is placed proximate to an input surface of the imager. 5 BRIEF DESCRIPTION OF THE FIGURES The invention may be understood from the following detailed description when read in connection with the following figures: FIG. 1 is a schematic illustration of a typical image intensifier tube, including an electron gain device and an electron sensing device. 10 FIG. 2a is a top view of an electron sensing device formed in a conventional manner, showing a ceramic header and bondwires. FIG. 2b is a sectional view of the electron sensing device shown in FIG. 2a. FIG. 2c is a sectional view of a conventional electron sensing device, is spaced in vertical proximity to and below an electron gain device, when integrated together in an image intensifier tube. FIG. 3a is a sectional view of an electron sensing device spaced below and in close vertical proximity to an electron gain device, in accordance with an embodiment of the invention. 20 FIG. 3b is a top cross-sectional view of a conductive epoxy/paste for electrically connecting the electron gain device to the header shown in FIG. 3a, in accordance with an embodiment of the invention. FIG. 3c is a cross-sectional view of a conductive epoxy/paste spanning between a CMOS device and a header, in accordance with an embodiment of the 25 present invention.
-8 FIG. 4 is a functional flow diagram showing various stages in making the electron sensing device of the present invention. DETAILED DESCRIPTION OF THE INVENTION Referring now to FIGS. 3a and 3b, there is shown an exemplary image 5 intensifier, generally designated as 50. Image intensifier 50 includes an electron gain device, designated as 52, for example a microchannel plate (MCP). Image intensifier 50 also includes an electron sensing device, designated as 56, disposed within ceramic substrate 60. Electron sensing device 56 may include, for example, a solid state CMOS (complimentary metal oxide semiconductor) sensor, a CCD (charge 10 couple device) sensor, or a hybrid electron bombarded CCD or CMOS sensor. As shown, electron gain device 52 is disposed above electron sensing device 56. The electron gain device includes an active region, generally designated as 62. It will be appreciated that the top surface of active region 62 includes an active receiving area sensitive to received electrons from a photocathode (shown as 15 16 in FIG. 1), the latter disposed vertically above electron gain device 52. Electron gain device 52 receives incident energy on its input surface and outputs amplified energy, as emitted electrons, on its output surface of active region 62. The output electrons are provided as an input to electron sensing device 56. For example, electron gain device 52, such as an MCP, generates several hundred electrons for 20 each electron entering at the input surface. As shown, active region 62 is disposed vertically above electron sensing device 56. The electron sensing device 56 receives the output electrons from electron gain device 52 and provides an output signal that is proportional to the amount of electrons received by the electron sensing device. Electrical connections - 9 are made between top surface 57 of electron sensing device 56 and top surface 58 of ceramic substrate 60. This is described further below. In accordance with an embodiment of the present invention, an electronic sensing device, for example CMOS device 56, is buried within ceramic 5 substrate 60, so that top surface 57 of CMOS device 56 is substantially coplanar with top surface 58 of ceramic substrate 60. It will be appreciated that CMOS device 56 includes an array of terminal pads disposed around the peripheral circumference of CMOS device 56. An exemplary array of terminal pads is shown in FIG. 2a designated as an array of terminal pads 36. The array of terminal pads 36 provides to various input/output (I/O) signals to or from the CMOS device. Similarly, an array of terminal pads is disposed on ceramic substrate 60. The array of terminal pads may be similar to the exemplary array of terminal pads 38, shown in FIG. 2a, disposed around the circumference of ceramic substrate 34. 15 As best shown in FIG. 3a, a plurality of pins 42 are extended from the bottom of ceramic substrate 60. The pins are electrically connected through via holes, for example, via holes 39a and 39b, to the array of bond pads disposed on top surface 58 of ceramic substrate 60. In accordance with the present invention, spans of epoxy/paste (where 20 only two are shown designated as 45a and 45b) are extended between the array of pads disposed on top surface 57 and the array of pads disposed on top surface 58. In this manner, electrical connections are made between the bond pads of CMOS device 56 and the input/output pins 42 of ceramic substrate 60. The electrical conductor epoxy/paste may be obtained by filling a 25 regular non-electrode conductor with a conductor material, such as silver, gold or carbide. External power sources and signal sources (for example, data and control - 10 signals) may be transferred to the CMOS device through the input/output pins placed at the bottom of the ceramic substrate. Because the CMOS device is buried within the ceramic substrate, the gap between the CMOS device and the output surface 62 of MCP 52 may be made s very small. For example, the gap may be made smaller than or equal to 0.005 inches. There are many ways to extend the electrical connections between CMOS device 56 and ceramic substrate 60. Referring to FIGS. 3a and 3c, there is shown an example of a span made of conductive epoxy/paste, designated as 45a, to which electrically connects bond pads 61 and 62. As shown, bond pad 61 is part of the array of bond pads formed on top surface 58 of ceramic substrate 60. Similarly, bond pad 62 is part of an array of bond pads formed on top surface 57 of CMOS device 56. As shown in FIG. 3c, spans 45a fills the gap between the ends of bond 15 pads 61 and 62. It will be appreciated that bond pads 61 and 62 are aligned so that when CMOS device 56 is inserted within the pocket formed in ceramic substrate 60, conductive epoxy/paste span 45a provides the electrical connection between the two bond pads. Bond pad 61 is electrically connected to at least one of the input/output pins 42 in ceramic substrate 60 and, similarly, bond pad 62 is electrically connected 20 to at least one function (not shown) performed by CMOS device 56. The array of bond pads formed on top of surface 58 and the array of bond pads formed on top of surface 57 may have any suitable shape, such as pads, strips, frames, or segments. In additions, the bond pads may be positioned at any desired locations on CMOS device 56 and ceramic substrate 60. 25 The span 45a may include many suitable materials, for example, span 45a may include an electrically conductive adhesive which may be a conductive - 11 epoxy. Specifically, the electrically conductive epoxy may be a standard epoxy filled with an electrically conductive material, such as metal elements (for example gold and silver), metalloids, or other material such as carbon, which by filling the standard epoxy results in a conductive epoxy, or carbides of metal elements. The 5 conductive adhesive may also include an electrically conductive organic (or polymer) material or an electrically non-conductive organic (or polymer) material filled with a conductive material. Each conductive epoxy/paste span 45a extends across gap 63 formed between a wall in the pocket of ceramic substrate 60 and a wall (or edge) of CMOS 1o device 56 (as shown in FIG. 3c). In order to provide additional support for electrically conductive span 45a, the present invention may include a non conductive paste, inserted as a filler in gap 63. The non-conductive paste is designated as 64 in FIG. 3c. Exemplary dimensions of a conductive span, formed between pad 62 is on CMOS device 56 and pad 61 on ceramic substrate 60 are provided in FIG. 3b. The width is shown as 0.010 inches (may vary between 0.002-0.012 inches). The length is shown as 0.025 inches (may vary between 0.015-0.050 inches). Referring now to FIG. 4, there is shown a functional flow diagram, depicting various stages in the making of the present invention. As shown, a first 20 stage may be the ceramic substrate without any pockets, generally designated as 71. The next stage may be ceramic substrate 71, after having been precision machined to form pocket 72. The final stage may be semiconductor device 73 (for example CMOS device 73) inserted within pocket 72 of ceramic substrate 71. A blow up of gap 63 formed between CMOS device 73 and ceramic 25 substrate 71 is shown at the bottom of FIG. 4. As shown, gap 63 may be - 12 constructed to provide a clearance of 0.005 inches, plus or minus 0.002 inches. Gap 63 may be filled with a non-conductive epoxy, such as epoxy 64 shown in FIG. 3c. The bonding process for connecting span 45a between bond pads 61 and 62 may be performed in many ways, according to the specific bonding agents 5 used. As an example, bond pads 61 and 62 may be aligned after insertion of CMOS device 56 within pocket 72 of ceramic substrate 71. Conductive electrical span 45a (and, of course, multiple other spans) may be deposited as paste or epoxy across gap 63 in order to electrically join bond pads 61 and 62. The bonding agent may then be cured at selective temperatures. The bonding agent may also be cured with 10 UV or (IR) light when the bonding agent includes UV or (IR) curable epoxy. After such curing, the span and the bond pads may also be pressed together with optional external pressure. The present invention may be used for any application that requires a close proximity between two devices, where physical clearance between the two is devices is an issue. The physical clearance issue does not necessarily have to result from bond wires looping above a top surface of a device, but may result from any physical body protruding above another body. Although the invention is illustrated and described herein with reference to specific embodiments, the invention is not intended to be limited to the 20 details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the invention.
- 12A In the claims which follow and in the preceding description of the invention, except where the context requires otherwise due to express language or necessary implication, the word "comprise" or variations such as "comprises" or "comprising" is used in an inclusive sense, i.e. to specify the presence of the stated' features but not to preclude the presence or addition of further features in various embodiments of the invention. A reference herein to a prior art document is not an admission that the document forms part of the common general knowledge in the art in Australia.

Claims (20)

1. An image intensifier comprising a microchannel plate (MCP) having an output surface, and a ceramic substrate having an outer surface, wherein the output surface of the MCP and the outer surface of the ceramic substrate are oriented facing each other, an imager is substantially buried within the ceramic substrate, and an input surface of the imager is exposed to receive electrons from the output surface of the MCP.
2. The image intensifier of claim 1 wherein the input surface of the imager and the outer surface of the ceramic substrate are oriented in substantially the same plane.
3. The image intensifier of claim 1 wherein the input surface of the imager and the outer surface of the ceramic substrate are disposed at a distance from the output surface of the MCP that is less than or equal to 0.005 inches.
4. The image intensifier of claim 1 wherein the imager includes input/output pads, the ceramic substrate includes other input/output pads, and a conductive epoxy connects a respective input/output pad of the imager to a respective input/output pad of the ceramic substrate.
5. The image intensifier of claim 1 wherein the imager includes input/output pads, the ceramic substrate includes other input/output pads, and - 14 multiple conductive epoxies connect multiple input/output pads of the imager to multiple input/output pads of the ceramic substrate.
6. The image intensifier of claim 1 wherein the imager includes a CMOS (complementary metal oxide semiconductor) device.
7. The image intensifier of claim 1 wherein the imager includes a CCD (charge coupled device).
8. The image intensifier of claim 1 wherein the ceramic substrate includes a pocket having a seat at a predetermined depth, the imager is configured to be received in the pocket, a bottom surface of the imager is disposed directly on top of the seat, and the top surface of the ceramic substrate and the input surface of the imager are substantially coplanar.
9. The image intensifier of claim 8 including a conductive epoxy spanning between (a) input/output pads disposed on the input surface of the imager and (b) input/output pads disposed on the top surface of the ceramic substrate for electrically connecting the imager to the ceramic substrate.
10. The image intensifier of claim 9 including a non-conductive epoxy deposited in the pocket, wherein the non-conductive epoxy is configured to fill gaps between (a) end surfaces of the imager inserted in the pocket and (b) walls of the pocket.
11. An image intensifier comprising an electron gain device having an output surface, - 15 an electron sensing device having an input surface, positioned below the output surface of the electron gain device, for receiving light from the output surface of the electron gain device, and a ceramic substrate disposed below the output surface of the electron gain device for housing the electron sensing device, wherein a top surface of the ceramic substrate is substantially coplanar with the input surface of the electron sensing device.
12. The image intensifier of claim 11 wherein the ceramic substrate includes a pocket for housing the electron sensing device, and the pocket is of a predetermined depth, so that the top surface of the ceramic substrate is substantially coplanar with the input surface of the electron sensing device.
13. The image intensifier of claim 11 including input/output pads disposed on the top surface of the ceramic substrate, input/output pads disposed on the input surface of the electron sensing device, and multiple conductive epoxy spans for electrically connecting the input/output pads of the ceramic substrate and the electron sensing device.
14. The image intensifier of claim 13 including non-conductive epoxy disposed below at least one conductive epoxy span for providing support to the at least one conductive epoxy span.
15. The image intensifier of claim 11 wherein the electronic sensing device is an imager, and the electron gain device is an MCP.
- 16 16. A method of making an image intensifier comprising the steps of: forming a pocket in a ceramic substrate; housing an imager in the pocket of the ceramic substrate; and spanning conductive epoxy between input/output pads of the ceramic substrate and the imager.
17. The method of making an image intensifier of claim 16 wherein the step of forming a pocket includes forming a seat in the pocket at a predetermined depth; and the step of housing includes placing the ceramic substrate on top of the seat in the pocket, so that a top surface of the imager is coplanar with a top surface of the ceramic substrate.
18. The method of making an image intensifier of claim 16 wherein the imager is either a CCD or a CMOS device.
19. The method of making an image intensifier of claim 16 including the step of: inserting a non-conductive epoxy in gaps formed between edges of the ceramic substrate and edges of the imager; wherein the step of spanning includes spanning the conductive epoxy in a horizontal direction across the gaps that have been filled with the non conductive epoxy.
20. The method of making an image intensifier of claim 16 including the step of: after housing the imager in the pocket of the ceramic substrate, placing an output surface of an MCP proximate to an input surface of the imager.
AU2009200888A 2008-07-10 2009-03-05 Electrical connection of a substrate within a vacuum device via electrically conductive epoxy/paste Abandoned AU2009200888A1 (en)

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US7880127B2 (en) 2008-10-27 2011-02-01 Itt Manufacturing Enterprises, Inc. Apparatus and method for aligning an image sensor including a header alignment means
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US5021888A (en) * 1987-12-18 1991-06-04 Kabushiki Kaisha Toshiba Miniaturized solid state imaging device
US5749830A (en) * 1993-12-03 1998-05-12 Olympus Optical Co., Ltd. Fluorescent endoscope apparatus
JP4098852B2 (en) * 1997-07-24 2008-06-11 浜松ホトニクス株式会社 Electron tube
US6335548B1 (en) * 1999-03-15 2002-01-01 Gentex Corporation Semiconductor radiation emitter package
US6483231B1 (en) * 1999-05-07 2002-11-19 Litton Systems, Inc. Night vision device and method
JP4179908B2 (en) * 2003-03-25 2008-11-12 フジノン株式会社 Imaging device
US7199345B1 (en) * 2004-03-26 2007-04-03 Itt Manufacturing Enterprises Inc. Low profile wire bond for an electron sensing device in an image intensifier tube
US7787170B2 (en) * 2004-06-15 2010-08-31 Texas Instruments Incorporated Micromirror array assembly with in-array pillars
US7482571B2 (en) 2005-08-01 2009-01-27 Itt Manufacturing Enterprises, Inc. Low cost planar image intensifier tube structure

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US20100006765A1 (en) 2010-01-14

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