AU2007214327B2 - Low power sinusoidal LC oscillator with amplitude stabilization - Google Patents

Abstract

P:\WPDOCS\KMHSpeafica o rver Ay One\20197604 spec doc-8/31/2007 An electronic circuit presented herein sustains a resonating characteristic on a parallel LC tank circuit for use in RFID (Radio Frequency IDentification) applications or other communication circuits requiring sinusoidal signal generators. The circuit which is 5 integrated into a sinusoidal oscillator tank driver stabilizes the oscillation amplitude by maintaining an optimum energy to compensate the power loss in the tank. The tank driver emits an excitation pulse in every oscillation cycle with the aid of an inbuilt negative feedback loop which optimizes the driving pulse width. The optimized pulse is obtained from the output of a comparator which compares between the RF signal at the tank and an 10 internal voltage reference signal. The reference signal tracks a level-shifted-up envelope of the RF signal for every oscillation cycle after which it is reset to the ground level at the negative peak of the RF signal. This reference signal adapts its comparing level so as to generate the minimum required pulse duration just to sustain the continuous oscillation for maximized power efficiency. 2 RF1 11 2 RF1 11 ................ 16 if17 16 a b Voltage - - 17 Voltage - - 18 - - I. I. 1 * I I -I 1 -1.1. time time Figure 6 19 20 21 22 3 RF1 Envel. Level Shift Buffer Comparator RF1 V Vrl Peak Detect V r. Vrese Driver dr Figure 7

Description

Australian Patents Act 1990 - Regulation 3.2 ORIGINAL COMPLETE SPECIFICATION STANDARD PATENT Invention Title Low power sinusoidal LC oscillator with amplitude stabilization The following statement is a full description of this invention, including the best method of performing it known to me/us: P/00/o I I c I n, P \WPDOCS\KMH\Spoficaobns\Drover Ay One\20197604 spectdoc-/31/2007 Low Power Sinusoidal LC Oscillator with Amplitude Stabilization Background of the Invention The invention proposed herein is related to a circuit arrangement to sustain the 5 oscillation of a parallel LC tank and to stabilize its sinusoidal signal amplitude. The circuit scheme can be applied to all passive-type RFID or other communication devices where the low-power consumption is suggested. Description of the Prior Art 10 The reference in this specification to any prior publication (or information derived from it), or to any matter which is known, is not, and should not be taken as, an acknowledgement or admission or any form of suggestion that that prior publication (or information derived from it) or known matter forms part of the common general knowledge in the field of endeavour to which this specification relates. 15 In a passive RFID system employing a RFID microchip with a LC resonant circuit or a "Tank" circuit, the RFID microchip only relies on the energy transmitted or induced from a RFID reader or an interrogator in the form of magnetic field coupling, therefore no energy or external power sources is required. A "RFID tag" or "tag" or widely known as a transponder, can be made in various forms depending on the application, it consists of a 20 microchip attached to the LC resonator circuit. The LC tank loads the reader's magnetic field and energizes the microchip generating a magnetic field feedback to the RFID reader. For example, in a sequential RFID system, the microchip gradually accumulates the RF field energy until the stored power reaches an adequate level before transmitting its FSK (Frequency Shift Keying) data back to the reader. After an appropriate energizing 25 time, the reader ceases to generate the magnetic field, the microchip then begins sending the data back to the reader in the form of RF magnetic field conforming to the protocol recognized by the reader. The reader decodes the data from the signal picked up at the reader antenna until the transponder completes the telegram. The communication through magnetic field is the key characteristic in the low frequency (100kHz -150kHz) and high 30 frequency RFID applications (1 3.56Mhz).

P \WPDOCS\KMH\Speafications\Drovers Ay On\20197604 specdoc-8/31/2007 -2 Despite the discontinuity of reader's excitation field, communications between the reader and the transponder can still be achieved because the LC tank still oscillates naturally at its self resonant frequency by using the energy stored in the inductor (L) and the capacitor (C). However, the generated RF field amplitude of the LC tank gradually 5 diminishes due to the energy loss associated with the inductor's parasitic resistance. Without an appropriate circuit to externally replenish the tank's dissipated energy, the oscillation eventually dies off, thus ending the telegram. An oscillator sustaining circuit that helps compensate the energy loss in the tank oscillator is then required to maintain the tag's complete communication with the reader. 10 A straight-forward approach to supply the energy to the tank is to drive the tank directly with a frequency synchronized square-wave signal. To limit a current flowing into the tank, a series resistor is most often inserted between the tank and the driver. However, this simple approach causes a considerable energy loss in the resistor resulting in tag's very high overall power supply consumption. In all passive RFID devices (no batteries 15 required), a large size capacitor storing sufficient energy for the tag is therefore imperative, requiring more energizing time to charge up. Consequently, the speed of the communication is greatly reduced. If it is a battery powered tag, the battery life is substantially shortened. Previously invented, two granted Patents describe oscillator maintaining 20 techniques. Both address methods of minimizing the power loss through a timing control which drives the LC tank. The US Patent 5227740, "Oscillation maintenance circuit", the power loss is reduced by a technique called "plucking". The said circuit technique detects and sets a switch to charge the tank in a short period duration. The proposed circuit improves the oscillator's efficiency by choosing a right "plucking" timing interval while 25 maintaining a tank oscillation. A further improved version of the "plucking" approach has been demonstrated later in Patent 5621396, "Method and apparatus with adaptive transponder plucking". The energy loss is further reduced by an adaptive plucking technique. The concept is to pluck the similar switch charging the voltage to the tank only when the oscillation amplitude is reduced to a certain level or when a preset number of 30 cycles are reached.

P:\WPDOCS\KMHSpeafications\Drer Ay C'ne\20197604 speci doc-8/31/2007 -3 The invention herein, a new LC tank low-power oscillator circuit is introduced which incorporates a new oscillation sustaining method for LC tank oscillator. In contrast to the above prior arts, this invention is a derivative of the circuit that drives the square wave signal to the tank to compensate for the energy loss. It minimizes the loss by 5 optimizing the tank's pulse driving square-wave interval while simultaneously keeping the oscillating amplitude optimized and regulated proportionately to the microchip's supply voltage. Summary of the Invention 10 The proposed invention a "low-power sinusoidal LC oscillator with amplitude stabilization" relates to a circuit configuration that maintains the LC tank resonating to continuously generate the RF magnetic field required by the RFID transponders' telegram. This invention can be used as a part of the RFID microchip both in passive transponders which utilizes the energy from the reader through induction coupling, and in active 15 transponders built with their own energy sources or batteries. Regardless of the types of transponders, both require a sinusoidal oscillator that must consume minimum power from the supply source while offering a good stability to the sinusoidal signal maintained over the tank. The invented circuit improves the energy loss by adjusting the pulse width of the square-wave signal driving the tank to an optimally adequate value. Furthermore, it 20 controls the oscillation amplitude by introducing a feedback loop which automatically senses and regulates the oscillator's both positive and negative output voltages in every cycle to fine tune the square-wave pulse duration. The proposed invention herein holds important configurative appearances consisting of a comparator generating a square-wave driving signal to the LC tuned circuit. 25 By comparing the tank oscillator's level to an adaptive reference signal, which keeps tracking the oscillation amplitude, renders the oscillator's immunity to transistor's threshold voltage shifts. The other object of the invented circuit further consists of a feedback control system wherein an envelope detector and a peak detector together govern the waveform of 30 the adaptive reference signal. The output of the envelope detector is level shifted becoming a decision point for the adaptive reference signal to track, while the output of the peak P :WPDOCS\KMFASpecficatons\Drovers Ay One\20197604 spec doc-8/1/2007 -4 detector is used for resetting the adaptive reference signal at every peak of the oscillation. The entire feedback loop is designed such that it limits the driving duty cycle to less than a quarter of an oscillation period in order to synchronize with the natural oscillatory timing to minimize unnecessary energy loss due to the current flowing in the driver. 5 In one broad form, the present invention provides an oscillator, designed for using with an LC tank to create a sinusoidal waveform whose amplitude is stabilized, consisting of an envelope detector (19) whose output (Venv) tracks the bottom of the signal RF 1 and RF2, a level shifter (20) offsetting the envelope detector output (Venv) to create a guideline for the reference level (Vref), a negative peak detector (23) generating a reset 10 signal (Vreset) by comparing the signal RF2 to the envelope signal (Venv) at the bottom peak of the signal RF2, a resettable Buffer (21) whose output, which always follows the shifted envelope signal (Vshf), is reset every period by the reset signal (Vreset), a comparator (22) comparing the reference signal (Vref) which is the output of the resettable buffer (21) to the signal RF2, a Driver (24) driving the LC tank as a load using a driving 15 signal (Vdrv) from the comparator intentionally designed to drive with a well controlled pulse width and optimum timing to save the energy loss. Preferably, the oscillation amplitude is stabilized by allowing the reference voltage (Vref) to track the bottom envelope of the oscillation signals (RFI, RF2), creating a negative feedback loop sensing the oscillation amplitude to control the driving signal's 20 negative-going pulse width. Also preferably, the oscillator (3) contains transistors (25-27), a current source (28), and a capacitor (34) altogether performing envelope detection, level shifting, and peak detection, and also contains transistors (29-32), a current source (33), and a capacitor (35) altogether composing a voltage buffer, and further contains transistors (36-43), and a 25 current source (42) making up a current different comparator, and finally contains a transistor (16) driving the LC tank. Brief Description of the Drawings The present invention will become more fully understood from the following 30 detailed description of preferred, but non-limiting embodiments thereof, described in connection with the accompanying drawings wherein: P.WPDOCS\MH\Speaficatons\Dovrs Ay Cn\2019764 speak doc-B/31/2007 -5 Fig 1. An analog front-end of a RFID microchip used in sequential RFID applications; Fig 2. An implementation of a full-wave rectifier with cross-coupled NMOS transistors; 5 Fig 3. An implementation of a full-wave rectifier with cross-coupled PMOS transistors; Fig 4. Waveforms of signals RFl, RF2 and a supply voltage HV from a full wave rectifier in Fig. 2; Fig 5. Waveforms of signals RFI, RF2 and a supply voltage HV from a full 10 wave rectifier in Fig. 3; Fig 6. A straight-forward method for sustaining the oscillation; Fig 7. A block diagram of the proposed oscillator; Fig 8. Waveforms of Venv, Vshf, and Vreset signals corresponded to RFI and RF2 signals; 15 Fig 9. Waveforms of Vcnv, and Vref signals corresponded to RF 1 and RF2 signals; Fig 10. Waveforms of Vdrv signals corresponded to RFI and RF2 signals; and Fig 11. An implementation of the invented oscillator. 20 Description of the Preferred Embodiments A known front-end circuit of a RFID microchip that requires an oscillation sustaining for sequential RFID applications is shown in FIG. 1. More specifically, major parts of the front-end comprise a bridge rectifier 1, an oscillator 3 embodying the LC tank, and an energy-storage device 9 (can be resided external off chip). A bridge rectifier 1 25 extracts a DC supply voltage from an AC signal coupled from the reader by the LC tank 2. The magnetic field coupled from the reader induces a current in the inductor and excites an oscillation on the tank. Due to energy losses in parasitic resistance of the tank elements, after the reader stops the exciting field, the tank oscillation amplitude decays naturally until it completely stops oscillation. The OSC circuit 3 hence is essential to help 30 compensate the loss by supplying the needed energy to maintain the oscillation. However, in doing so, the compensation draws the energy from the energy storage device 9 which P\WPDOCS\KMH\Specficatons\Dres Ay Cne\20197504 spec doc-8/31/2007 -6 can be of an on-chip supply's decoupling capacitor 45 together with an external supply decoupling capacitor or even an external battery 46. In other words, the oscillator transfers the energy from the energy source 9 (DC supply) to the tank 2 (AC signal) thus compensating the loss. 5 The oscillator topologies and their implementations can widely vary depending on the types of bridge rectifier 1 structure and configuration, e.g. using cross-coupled NMOS transistors and two diodes as appeared in FIG. 2, or its counterparts in FIG 3. In this invention, for CMOS integrated circuit approach, only the implementation of the OSC 3 that suits to the rectifier in FIG. 3 is opted. For the rectifier 4 in FIG. 2, the 10 oscillator schematic can be constructed using counterpart devices of the circuit that will be illustrated in upcoming paragraphs which is well understood by a person working in this field. A rectifier 4, as shown in FIG. 2, consists of two NMOS transistors 5 and 6 arranged in a cross-coupled manner, and two diodes 7 and 8 sharing their cathodes. In 15 known general CMOS fabrication process, these diodes can be created from a junction between P-diffuse and N-well layers. This structure, having the ground reference at their source terminals, gives the AC signal on the tank RFI, RF2 as depicted in FIG. 4 whereby the difference between the signal RFI and RF2 is a sinusoidal waveform. Conceptually, when the signal RFI rises above the ground, a NMOS transistor 6 turns on connecting the 20 signal RF2 to the ground. At the signal RFI's peak, the diode 7 is forward biased allowing a current to flow from the tank 2 into the energy storage device 9 whereby a DC supply voltage HV is being accumulated. This operation is also called rectifying of AC to DC. Both transistor 5 and diode 8 are off when the signal RFI becomes positive. Over the next half cycle, the operation of all devices are reversed. The signal RF2 rises above the ground 25 and turns on the other NMOS transistor 5 connecting the RFI to ground. The reverse is also true for the other devices 6-8. After the readers' magnetic field ends at time ti, the amplitude of the RF and RF2 will decay insofar as the HV level is still kept up by the energy source 9. Another rectifier 10 disclosed herein is shown in FIG. 3. The rectifier 10 consists of 30 two PMOS transistors 11, 12 arranged in the cross-coupled manner and two diodes 13, 14 formed by a P-N junction between P-substrate and N-diffuse layers (or P-diffuse and N- P kWPDOCS\KMFISpe icatfons\Drovers Ay One\20197604 speci doc-8/31/2007 -7 well layers). The rectifier 10 operates similarly to the rectifier 4 described previously. However, the signal RFI and RF2 are now referenced to the supply voltage HV voltage where as their waveforms are mirrored over as shown in FIG. 5. For present invention, further objects and discussions about the circuit diagram of 5 the OSC 3, although not exclusively, are explained in conjunction with the rectifier 10. FIG. 6a shows one of the most commonly known methods to sustain the oscillation of a LC resonator. The sustaining mechanism is based on driving the tank 2 with a square wave 17 through a push-pull or a class-B driver consisting of pair of complementary transistors, for instance, a NMOS 15 and a PMOS 16. The square wave 17 controlling the 10 driver is simply generated by comparing the signal RF2 to RF 1. However, one can postulate that the method in FIG. 6a is inefficient because a large amount of energy loss of the driver is mostly due to excessive harmonic spectrums during the tank being hard driven. To reduce the energy loss, the conducting period of the transistor 16 must be intentionally made narrow by limiting the negative pulse interval of the square wave 17 15 (the meaning in this disclosure is inverse polarity as opposed to a normal positive going pulse to suit the active-low nature of PMOS transistor). A predetermined synchronized pulse period of 18 suitable for optimized power scheme is then proposed. In addition to the power saving benefit, the negative pulse width is also a main contributor to the oscillation amplitude thus the OSC 3 complete circuit also incorporates an amplitude 20 stabilizer. FIG. 7 illustrates the circuit configuration of the OSC 3's block. The invented circuits operate on a relationship principle of the driver characteristic and the tank's large signal response. One can observe from Fig. 6a more specifically that only the PMOS 16 conducts during time periods 48 while during time period 49 both MOS 15 and 16 are in cutoff state. Consequently, the NMOS 15 can be neglected because it 25 operates on the cutoff region for most of the time. Optionally, one can add another complimentary driver to drive an inverse square wave of 17 to the other tank 2's terminal (RFl) since the differential drivers can increase the oscillation amplitude, although only slightly. In FIG. 6, only the devices that are active during the time period 48 are considered. Accordingly, the rectifier 10 in Fig. 3 can be deliberately reduced to render 30 only PMOS 11 for operation during the RF2 signal falling below the voltage IV.

P:WPDOCS K SpecincatoS\rvers Ay One\20197604 specdoc-8/31/2007 The invention's OSC 3 schematic diagram is illustrated in FIG 7. The OSC consists of an envelop detector, a level shifter, an adaptive peak-sensing buffer, a comparator, and an optimized driver. The envelope detector 19's obtained output, Venv, is level-shifted up by a level shifter 20, monitors the RFl and RF2 bottom peaks as depicted in FIG. 8. This 5 envelope shifted up signal derived as a guiding level, Vshf, is used to lead the buffer's subsequent reference signal, Vref, to follow. The buffer which generates the reference signal Vref, however, possess a special attribute in that its output can be reset to the ground level every cycle by a reset signal Vreset derived from the Peak Detector. Consequently, the RFI and RF2 peak information is updated on cycle-to-cycle basis resulting in the 10 amplitude of the oscillator to be kept stabilized. To generate the cycle reset signal, the envelope Venv is compared to the bottom peak of the signal RF2 by the Comparator 23. Note that only one RF pin is sufficiently accurate for the task of creating this Vreset because the oscillator's peak at RFl in between RF2's consecutive cycles is marginally different. However, the choice of RF signal level 15 detection must be in synchronization of the driver's polarity for the reset signal, Vreset, to create an optimum driving pulse for the Driver 24. Otherwise, more oscillator amplitude ripples can most likely occur. Despite the Vreset being generated by one RF side, the Vref in between the cycle resetting action can still track the envelope shifted signal Vshf. During the Vreset going 20 high (represented by the voltage HV), the Vref will be drawn to the ground level as shown in FIG.9. The Comparator 22 creates a negative-going Vdrv, as shown in FIG. 10, by comparing potentials between the Vref of the level-resettable Buffer 21 at its negative input and the incoming RF2 signal at the positive input. The Vdrv's pulse duration is therefore wide or narrow in proportional to the potential difference between these two 25 signals, i.e., the more the voltage difference the wider the driving pulse duration. The entire OSC 3 loop thus maintains the oscillation amplitude practically to a constant. The Driver 24 is in fact reduced in its full configuration to a single transistor as discussed earlier in FIG. 6b. As soon as the Vdrv switches from HV to the ground, while the RF2 signal still steers its negative falling direction further downward, the 30 synchronizing Vdrv pulse is then proportionately achieved. The pulse width determines the degree of how the oscillator should be compensated for its cycle-to-cycle amplitude P \WPDOCS\KMHSpeaficatonsDrves Ay On\201l97604 spec doc-&31/2007 -9 reduction. The wider the Vdrv width, the more the energy the tanks 2 requires to excite. This operation compensates the coil's inherent energy loss and sustains the tank's oscillation. If the oscillation amplitude decays, the decrease in the oscillator amplitude gives 5 rise to the Vref since the envelope signal Venv tracks the upward rising of the RF signal's bottom. Higher reference levels causes the Vref to intercept with the signal RF2 faster resulting in a widening Vdrv pulse width. Accordingly, the driver will draw the negative going signal RF2 more strongly in the direction to increase the oscillation amplitude. The reference level Vref, on the other hand, keeps monitors the overall oscillator amplitude and 10 decreases its level to approach a steady state. This negative feedback mechanism also applies in the reverse direction when the oscillation amplitude is too large. The amplitude increase causes the Vref to become lower, hence the Vdrv pulse width gets narrower. The small driving pulse period excites the tank very minimally allowing the oscillation amplitude to decay, which eventually settles to an 15 almost constant amplitude. Another object of the invention in the oscillator of FIG. 7 is to render the amplitude stabilizing mechanism provided by the negative feedback loop. This added advantage permits the oscillation to be robust and immune to several external variation sources such as fabrication process, inductance, capacitance, and antenna quality factor. 20 The overall conceptual diagram in FIG. 7 of the present invention is realized as an integrated circuit implementation shown in FIG 11. The envelope detector 19, the level shifter 20, and the peak detector 23 are combined into a single circuit block. PMOS transistors 25-27 together with a current source 28 and a capacitor 34 detect the envelope of the signal RF1 and RF2. The envelope signal is internally level-shifted up to 25 the envelope shifted signal, Vshf, by a gate-source voltage of PMOS transistors 25 and 27. The PMOS 26, acting as a switch, helps the Buffer 21 to track its input Vshf quickly after resetting of the Vref is achieved by feed-forwarding the input to the output. The current source 28 and the capacitor 34 define the time constant of the envelope detector 19, i.e., how fast the detector can track the change in the RF signal's amplitude. 30 The PMOS transistor 25 also simultaneously compares the RF2 signal to the envelope signal Venv. If the RF2 level is lower than the Venv, PMOS 25 conducts a P \WPDOCS\KMH\Spooficatons\Drovers Ay One\20197604 spec doc-8/31/2007 - 10 current provided by the current source 28 which also then flows into the Buffer 21. This current is mirrored by loaded transistors 31 and 32 of the Buffer 21 to pull the Buffer output (Vref) down to the ground. The Buffer 21 is implemented by a regular differential pair connected in a unity-gain feedback style. The circuit consists of an input transistor pair 5 29, 30, a current mirror 31, 32, a current source 33, and a bandwidth limiting capacitor 35. Transistors 36-44 are connected in a form of a current-mirror different amplifier with its positive-input transistor 37 is attached to the signal RF2 and its negative-input transistor 36 attached to the reference signal Vref. A current developed in the transistor 36 is mirrored twice by current mirrors 38, 40 and 42, 43, while the current of the transistor 10 37 is mirrored once by the current mirror 39, 41. Both currents are subtracted and converted into the output voltage Vdrv. The Driver 24 is implemented by a single PMOS 16 which drives the tank 2 at RF2 pin using negative going polarity. The reference numerals in the following claims do not in any way limit the scope of the respective claims. 15 Whilst the present invention has been herein described with reference to preferred embodiments thereof, it will be understood by persons skilled in the art that numerous variations and modifications may be made thereto. All such variations and modifications should be considered to fall within the scope of the invention as broadly hereinbefore described, and as hereinafter claimed.

Claims (4)

1. An oscillator, designed for using with an LC tank to create a sinusoidal waveform whose amplitude is stabilized, including an envelope detector whose output (Venv) tracks 5 the bottom of the signal RFI and RF2, a level shifter offsetting the envelope detector output (Venv) to create a guideline for the reference level (Vref), a negative peak detector generating a reset signal (Vreset) by comparing the signal RF2 to the envelope signal (Venv) at the bottom peak of the signal RF2, a resettable Buffer whose output, which always follows the shifted envelope signal (Vshf), is reset every period by the reset signal 10 (Vreset), a comparator comparing the reference signal (Vref) which is the output of the resettable buffer to the signal RF2, a Driver driving the LC tank as a load using a driving signal (Vdrv) from the comparator intentionally designed to drive with a well controlled pulse width and optimum timing to save the energy loss. 15

2. The circuit arrangement of claim 1 in which the oscillation amplitude is stabilized by allowing the reference voltage (Vref) to track the bottom envelope of the oscillation signals (RF 1, RF2), creating a negative feedback loop sensing the oscillation amplitude to control the driving signal's negative-going pulse width. 20

3. The circuit arrangement of claim I characterized in that the oscillator includes transistors, a current source, and a capacitor altogether performing envelope detection, level shifting, and peak detection, and also includes transistors, a current source, and a capacitor altogether composing a voltage buffer, and further includes transistors, and a current source making up a current different comparator, and, finally includes a transistor 25 driving the LC tank.

4. An oscillator, substantially as herein described with reference to the accompanying drawings.