AU2006292011B2 - A method and apparatus adapted to demodulate a data signal - Google Patents

Abstract

The present invention relates to the field of receiving data and/or demodulating a data transmission signal. The present invention provides a method of and/or device for determining a data signal imposed on a phase jitter modulation signal. In one form, the invention relates to the field of Radio Frequency Identification (RFID), and the transmission of data between a tag and an interrogator.

Description

WO 2007/030860 PCT/AU2006/001316 1 A METHOD AND APPARATUS ADAPTED TO DEMODULATE A DATA SIGNAL FIELD OF INVENTION The present invention relates to the field of receiving data and/or 5 demodulating a data transmission signal. In one form, the invention relates to the field of Radio Frequency Identification (RFID), and the transmission of data between a tag and an interrogator. In another form, the present invention is suitable for recovering data 10 received by a tag. The data signal is imposed on a carrier signal, for example a powering signal, received via an antenna. It will be convenient to hereinafter describe the invention in relation to a signal received by a tag from an interrogator, however it should be appreciated that the present invention is not limited to that use only. 15 BACKGROUND ART The discussion throughout this specification comes about due to the realisation of the inventors and/or the identification of certain prior art problems by the inventors. The inventors have realised that in the past, data has been transmitted to 20 RFID tags by modulation of the excitation field. Generally pulse position modulation (PPM) is used, where 100% depth amplitude modulation of the interrogation field is used. The interrogation field is turned off for short pulse periods and this is detected by the tag's processing circuitry. The inventors have realised that to achieve high data rates whilst 25 maintaining the transmission of power, these pulses must be short and the duty cycle must be low. Typically a duty cycle of approximately 10% is used where the pulses are 9ps long and the average time between pulses is around 75ps. An example of such systems is provided by ISO14443 The inventors have further realised that additionally, PPM produces 30 relatively high level modulation product side bands. For passive tags, a stronger excitation field is required to compensate for a less efficient antenna. Emission regulations must also be kept in mind and these place restrictions on side band transmissions including modulation products that can be transmitted. This places WO 2007/030860 PCT/AU2006/001316 2 restrictions on the maximum excitation field strength that can be used. In order to reduce the sideband levels the modulation depth can be reduced. Modulation depths of between 10% and 30% have been proposed. An example of such a system is provided by IS018000-3 Mode 1 and an internationally recognised 5 RFID system. For these small modulation depths the tag voltage regulation circuits connected to the tag antenna will reduce the amplitude detected by the tag through the effect of amplitude compression. The stronger the interrogation field the greater the level of amplitude compression. However, amplitude compression of the PPM signal leads to a much reduced operating range for 10 systems using PPM. Any discussion of documents, devices, acts or knowledge in this specification is included to explain the context of the invention. It should not be taken as an admission that any of the material forms a part of the prior art base or the common general knowledge in the relevant art in Australia or elsewhere on or 15 before the priority date of the disclosure and claims herein. An object of the present invention is to provide an improved data reception and/or demodulation method and apparatus. A further object of the present invention is to alleviate at least one disadvantage associated with the prior art. 20 SUMMARY OF INVENTION The present invention provides a method of and/or device for determining a data signal imposed on a Phase Jitter Modulation (PJM) signal, the method comprising the steps of providing a first phase jitter modulated signal, applying a delay to the first signal, and obtaining a second signal, comparing the first and 25 second signals, determining the phase difference between the first and second signals, and reconstructing a data signal based on the phase difference. Other aspects and preferred aspects are disclosed in the specification and/or defined in the appended claims, forming a part of the description of the invention. 30 Whilst, the inventors have realised that as an alternative to PPM, phase modulation has significant advantages in that bandwidth is narrower compared to PPM and thus significant data rate increases are possible. The detection of a phase modulated signal would typically be performed by a PLL. The inventors WO 2007/030860 PCT/AU2006/001316 3 have realised that the purpose of a PLL in a prior art circuit is in effect to provide a stable phase reference. But in practice, although the phase of the PLL does not move quickly, -but it does move slowly (drift), in a data dependant manner, resulting in intersymbol Interference (ISI). The phase of a PLL may also be 5 'moved' a little in response to a noise spike, for example. These spikes also cause noise at the circuit output as the PLL re-adjusts itself. In the present invention, a relatively fixed reference is.provided in a form which is considered to be relatively more stable, offer lower noise and is relatively more adaptable for ASIC integration. 10 The present invention -relates to an improvement on the method and apparatus disclosed in co-pending applications based on PCTIAU98/01077, the disclosure of which is herein incorporated by reference. PCT/AU9801077 discloses the use of a Phased Locked Loop (PLL) as a part of the demodulation circuitry. it has been realised by the inventors that the PLL tends to 'drift' in 15 response to an input change in the PJM signal. This is known to cause Inter Symbol Interference (ISI). The inventors have further found that a PLL may tend to suffer from noise associated problems, and that an improved form of signal detection is required as the signal being demodulated in order to obtain data is relatively weak as compared to the carrier signal. It would be also advantageous 20 if the demodulation circuit is more readily adapted for VSLI, integration into 'chip' form. The present invention provides a relatively fixed reference in the form of a delay, such as a delay line. A delay, and implemented in a PJM detector, according to the present Invention has been found to not drift; it is relatively 25 'fixed'. Tests have found that in response to a noise spike, the noise simply propagates the delay line, without substantial effect on the delay time. In tests of the present invention, improved noise performance has been found to be in the order of approx 20dB less noise compared to an equivalent PLL. In the present invention, a delay line (DLL) is used and it operates within 30 the data demodulation circuit to assist in the detection of Phase Jitter Modulation, but substantially without distorting the signal from which the data is to be obtained. The DLL may detect phase edges, such as by way of a window detector.

WO 2007/030860 PCT/AU2006/001316 4 The present invention is applicable to various forms of tag(s) and/or interrogator(s). Thus, the nature of the data transmitted according to the present invention is not essential and the tag and / or interrogator whether active and/or passive is not essential to the present invention. A tag may be a transponder. 5 The present invention has been found to result in a number of advantages, such as: * Relatively low noise * Relatively little ISI, and in many cases, no ISI * Relatively simple to implement in ,an ASIC 10 * The circuit implementation is relatively stable in operation, * Relatively small area on silicon, and * Uses conventional devices and production processes Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood 15 that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description. BRIEF DESCRIPTION OF THE DRAWINGS 20 Further disclosure, objects, advantages and aspects of the present application may be better understood by those skilled in the relevant art by reference to the following description of preferred embodiments taken in conjunction with the accompanying drawings, which are given by way of illustration only, and thus are not limitative of the present invention, and in which: 25 Figure 1 illustrates a circuit disclosed in PCT/AU98/01077, Figure 2 illustrates the various signals and waveforms associated with the operation of the circuit of Figure 1, Figure 3 provides a schematic representation of the present invention, Figure 4 illustrates an embodiment of the present invention, 30 Figure 5 illustrates another embodiment of the present invention, Figure 6 illustrates yet another embodiment of the present invention, WO 2007/030860 PCT/AU2006/001316 5 Figures 7a and 7b illustrate the various waveforms associated with the present invention, Figure 8 illustrates one embodiment of a window detector according to one embodiment of the present invention, 5 Figure 9 shows actual waveforms associated with the circuits shown in Figure 6 and Figure 8, Figure 10 shows an embodiment of the invention that uses a digital vernier to directly detect the PJM signal, and Figures 11 A and 11B show two embodiments of a delay line applicable to 10 the present invention. DETAILED DESCRIPTION Referring to Figures 1 and 2 together, the signal 1 represented in Figure 2 is a phase signal formed on a carrier signal 2 which is modulated excitation 3 input in Figure 1. Figure 2 illustrates more clearly the phase signal I which is 15 imposed on the carrier signal 2 of.Figure 1. Also illustrated in Figure 1 is a Phase Locked Loop (PLL) tracking signal 4. That is the effect of the phase signal on the circuit configuration of Figure 1, in operation, is that the PLL 'drifts'. Also illustrated in Figure 2 is a representation 6 of an 'ideal' recovered signal from the output of the XOR gate 5 of Figure 1. However, in practice, the 20 recovered signal from the output of the XOR gate 5 in Figure 1 is more like signal 7 illustrated in Figure 2. In Figure 2, the difference between the 'ideal' signal 6 and the actual recovered signal 7 is shown, in part, by numerals 8 and 9. This difference is referred to as ISI. The inventors have found that the PLL has an inherent operational transient response which causes ISI. The problem(s) 25 associated with ISI are: * Distorts the recovered waveform . Moves recovered data edges from a correct position depending on the preceding recovered data Figure 3 illustrates schematically the present invention. In essence, in one 30 aspect, the use of a delay in the demodulation of the PJM signal, has been found to overcome the problem of signal distortion. As illustrated in Figure 3, the 'shape' phase signal I which forms an input signal 10 to the delay 1-1 is relatively WO 2007/030860 PCT/AU2006/001316 6 preserved when observing the delayed signal 12 at the output 13. Compare.this with the 7 as shown in Figure 2. Figure 4 illustrates a relatively basic representation of one embodiment of the present invention. A PJM signal 41 having a phase modulated signal applied 5 to a carrier signal Fo is applied to an input 42 of the demodulation circuit according to the present invention. The applied signal is delayed 43, providing a delayed signal 44 which is input to a differential phase detector 45 together with a further input signal provided on path 46., In one embodiment, the differential phase detector obtains an output signal 2Fo + data. This mixer output is applied 10 to a Low Pass Filter (LPF), and the resultant (output) from the differential phase detector is the data signal. In one form, it is preferred that the delay 43 is shorter than the bit interval of the PJM signal 41. In another form, and with the PJM signal at a carrier frequency of 13.56MHz, a delay of approximately 10 carrier cycles has been 15 found to perform well, but which does vary with the data rate. In yet another form, setting the delay to substantially half or less of the bit interval of the (data) signal 41 has been found to enable operation of the present invention. In yet another form setting the delay to % or less of a bit interval has been found to enable operation of the present invention. The differential phase detector may comprise 20 an XOR gate and a LPF. Alternatively, the phase detector may be any one or a combination of any of a digital vernier, mixer, multiplier or XOR gate. Figure 5 illustrates a further embodiment of the present invention. A PJM signal is applied at input 52. A delay line may comprises, for example a fixed delay (DLL) 53 and a variable delay 54. The purpose of the variable delay 54 will 25 be detailed shortly. It has been found by the inventors that for optimum operation, the phase angle difference a' between the delay line 53/54 and path 56 should be maintained in the linear portion of the phase detector's characteristics. For an XOR gate this is between 0* and 180*, most preferably 90*, or between 1800 and 3600, most preferably 270*. For an XOR gate 30 operation around or close to 0*, 180* or 3600 should be avoided as the slope of the phase characteristic changes sign leading to distortion in the recovered phase signal. The purpose of the variable delay 54 is to ensure, in operation of the present invention, that the difference a* is not close to 0*, 180" or 3600.

WO 2007/030860 PCT/AU2006/001316 7 Preferably the variable delay maintains the difference a* around substantially 900 or 270*, although, as described above, the delay or phase angle may be anywhere between 0* and 180* or 180* and 3600. Other phase detectors may have different characteristics and the purpose of the variable phase delay would 5 be to operate these detectors in 'good' regions of their detection characteristics and away from 'bad' regions, The differential detector 45 of Figure 4 is represented as an XOR gate 55 and a LPF 57. Other suitable arrangements may be used as a differential detector, such as an analogue mixer or analogue multipliers. 10 Figure 6 illustrates a further embodiment of the present invention, in which the adjustable delay 54 of Figure 5 is represented as a number of selectable delays 64 by way of switches A, B, C or D. Only one switch is selectable in the arrangement illustrated. Delays 64a, 64b, 64c may be selectable or predetermined as required by the particular application. For example, the delays 15 64a, 64b and/or 64c may be substantially 450. Switch A, when closed serves to have the present invention provide a delay a" of only DLL 63. Switch B, when closed serves to have the present invention provide a delay a* of DLL 63 and DLL 64a. Switch C, when closed serves to have the present invention provide a delay a of DLL 63, DLL 64a and DLL 64b. Switch D, when closed serves to have the 20 present invention provide a delay a* of DLL 63, DLL 64a, DLL64b and DLL64c. In this way, the phase angle difference a* can be maintained between- 0* and 1800 or between 1800 and 3600 but not close to 00, 180* or 3600. This embodiment has been designed with ASIC integration in mind also. It has been realised by the inventors that an exclusive OR gate (XOR gate) 65 is 25 readily integratable, and that a delay DLL 63, 64, etc and switches A to D are all relatively easily integratable. Moreover a short delay of less than one bit period and preferably % or less of a bit period is relatively easily integratable. Figure 7a illustrates the various waveforms of the present invention. There is an input waveform 71 (for example as applied to input 62 of Figure 6), a 30 delayed waveform 72 (for example on path 68 in Figure 6), having a delay D with a phase angle difference a 0 (maintained between 0* and 1800 or between 1800 and 3600 but not close to 0*, 1800 or 3600), and a resultant 2 Fo + data waveform WO 2007/030860 PCT/AU2006/001316 8 73, where the data is present as relatively small changes in the duty cycle of the waveform 73. Figure 7b illustrates a phase angle of the PJM data 74, the phase of the signal delayed by delay line length D is shown as 75 and the output of the LPF 5 filter (which is relatively small in amplitude as compared to the PJM signal) is shown by 76. The output 76 consists of a discrete phase differential of the PJM signal with a positive voltage pulse produced by a positive phase change and a negative voltage pulse produced by a negative phase change The output of the LPF, for example LPF 67 of Figure 6, may be input into a 10 window detector. Figure 8 illustrates one embodiment of a window detector. The waveform 76 is applied to input c of Figure 8 and the average DC value of wave form 76 is applied to DC fix input of Figure 8. The comparator 81 and 82 then detect the positive and negative going pulses of 76. The positive pulse 'sets' the flip-flop 83 and the negative going pulses 'resets' the flip-flop 88. This results in a 15 waveform 77 in Figure 7, which is substantially the same as the PJM data 74. Figure 9 shows actual waveforms associated with the circuits shown in Figures 6 and Figures 8. The PJM data (first trace) is used to PJM modulate a signal resulting in the phase modulated signal shown (second trace). The recovered signal at the output of the LPF is shown (third trace) and consists of 20 positive and negative pulses, the pulses being filtered by the action of the LPF. The data recovered by a window detector is then shown (fourth trace). Figure 10 shows an embodiment of the invention that uses a digital vernier to directly detect the PJM signal. The digital vernier adjusts the phase of the delayed PJM signal so that it exactly coincides with the phase of the PJM signal 25 with no delay. The vernier circuits can then detect the tiny relative phase shifts that occur due to PJM. A digital vernier has the advantage of not requiring phase detecting element with a LPF. Figure. 11A shows an example of a delay line which uses a discrete resistance R and Capacitance C to achieve a small fixed delay td. If n stages are 30 concatenated, the total delay will be Tn = n t d. For example, where the invention is used in a 13.56MHz system, the 10 carrier cycles around 74OnSec. If R and C are chosen to give a lOnsec delay, then n=74 will give a total delay of 740nsec.

WO 2007/030860 PCT/AU2006/001316 9 Figure 11 B shows an example of a delay line which is readily integratable into an ASIC. The propagation delay through each inverter is td and the total delay for n stages is Tn = n td. td is set by designing the characteristics of the inverters, td can be adjusted 5 a small amount by varying the supply voltage to the inverter. While this invention has been described in connection with specific embodiments thereof, it will be understood that it is capable of further modification(s). This application is intended to cover any variations uses or adaptations of the invention following in general, the principles of the invention 10 and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains and as may be applied to the essential features hereinbefore set forth. As the present invention may be embodied in several forms without departing from the spirit of the essential characteristics of the invention, it should 15 be understood that the above described embodiments are not to limit the present invention unless otherwise specified, but rather should be construed broadly within the spirit and scope of the invention as defined in the appended claims. Various modifications and equivalent arrangements are intended to be included within the spirit and scope of the invention and appended claims. Therefore, the 20 specific embodiments are to be understood to be illustrative of the many ways in which the principles of the present invention may be practiced. In the following claims, means-plus-function clauses are intended to cover structures as performing the defined function and not only structural equivalents, but also equivalent structures. For example, although a nail and a screw may not be 25 structural equivalents, in that a nail employs a cylindrical surface to secure wooden parts together, whereas a screw employs a helical surface to. secure wooden parts together, in the environment of fastening wooden parts, a nail and a screw are equivalent structures. "Comprises/comprising" when used in this specification is taken to specify 30 the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof." Thus, unless the context clearly requires otherwise, throughout the description and the claims, the words 'comprise', WO 2007/030860 PCT/AU2006/001316 10 'comprising', and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to".

Claims (23)

1. A method of determining a data signal imposed on a phase jitter modulation (PJM) signal, the method comprising the steps of: 5 providing a first phase jitter modulated signal; applying a delay of less than one bit period to the first phase jitter modulated signal, and obtaining a second phase jitter modulated signal; comparing the first and second signals; determining a phase difference between the first and second signals; and 10 reconstructing a data signal based on the phase difference.

2. A method as claimed in claim 1, wherein the delay is a variable delay.

3. A method as claimed in claim 1 or 2, wherein the phase difference is 15 determined by an XOR gate.

4. A method as claimed in claim 1 or 2, wherein the phase difference is determined by a mixer. 20

5. A method as claimed in claim 1 or 2, wherein the phase difference is determined by a multiplier.

6. A method as claimed in claim 1 or 2, wherein the phase difference is determined by a digital vernier circuit. 25

7. A method as claimed in any one of claims 1 to 6, wherein the delay is less than half of a bit period.

8. A method as claimed in any one of claims 1 to 6 wherein the delay is less 30 than one quarter of a bit period. 12

9. A method as claimed in any one of claims 1 to 8 applied in an RFID system.

10. A device adapted to demodulate a data signal imposed on a phase jitter 5 modulation (PJM) signal, comprising: a receiver adapted to receiver a first phase jitter modulated signal; delay means adapted to apply a delay of less than one bit period the first phase jitter modulated signal, and obtaining a second phase jitter modulated signal; and 10 logic means adapted to compare the first and second signals, determine a phase difference between the first and second signals, and reconstructing a data signal based on the phase difference.

11. A device as claimed in claim 10, wherein the delay is a variable delay. 15

12. A device as claimed in claim 10 or 11, wherein the phase difference is determined by an XOR gate.

13. A device as claimed in claim 10 or 11, wherein the phase difference is 20 determined by a mixer.

14. A device as claimed in claim 10 or 11, wherein the phase difference is determined by a multiplier. 25

15. A device as claimed in claim 10 or 11, wherein the phase difference is determined by a digital vernier circuit.

16. A device as claimed in any one of claims 10 to 15 where the delay is less than half of a bit period. 30

17. A device as claimed in any one of claims 10 to 16 where the delay is less than one quarter of a bit period. 13

18. A device as claimed in any one of claims 10 to 17 being an RFID device.

19. A device as claimed in claim 18, the device being a tag, transponder or interrogator. 5

20. A RFID system including the device as claimed in any one of claims 10 to 19.

21. A method as claimed in claim 1, substantially as herein described with 10 reference to figures 3 to 11 B of the accompanying drawings.

22. A device as claimed in claim 10, substantially as herein described with reference to figures 3 to 11 B of the accompanying drawings. 15

23. A RFID system as claimed in claim 20, substantially as herein described with reference to figures 3 to 11 B of the accompanying drawings.