AU2006252249A1 - Bitmap data caching in a tile-based rendering system - Google Patents

Description

S&FRef: 786810

AUSTRALIA

PATENTS ACT 1990 COMPLETE SPECIFICATION FOR A STANDARD PATENT Name and Address of Applicant Actual Inventor(s): Address for Service: Invention Title: Canon Kabushiki Kaisha, of 30-2, Shimomaruko 3-chome, Ohta-ku, Tokyo, 146, Japan Krzysztof Adam Koziarz Spruson Ferguson St Martins Tower Level 31 Market Street Sydney NSW 2000 (CCN 3710000177) Bitmap data caching in a tile-based rendering system The following statement is a full description of this invention, including the best method of performing it known to me/us:- 5845c(619668 1) -1- BITMAP DATA CACHING IN A TILE-BASED RENDERING SYSTEM Technical Field The present invention relates to graphic object rendering and more particularly to efficient tile-ordered rendering ofbitmap images subject to an upscaling transformation.

Background In tile-based rendering systems, the page or screen to be output is rendered from display list (DL) primitives in a tile-by-tile fashion. That is, individual rectangular regions of pixels, or tiles, are rendered independently of other tiles. Typically, the output space is divided into tiles of a uniform pixel height and width. Tiles at the boundaries of the page or screen to be rendered may have a different size, or else be padded to the dimensions of non-boundary tiles.

Ordinarily, the generation or rendering of output tiles is either row or column sequential. That is, a complete row or column of tiles is rendered before rendering the next row or column of tiles. Alternatively, tiles may be rendered in a random fashion, or multiple tiles may be rendered in parallel.

Efficient caching of bitmap display list primitives is highly desirable in tilebased rendering systems. A particularly desirable feature of limited memory systems, for example, is that bitmap display list primitives be stored in a compact form relative to the total size of raw source pixel data. To reduce the size of bitmap primitives in memory, data compression is typically applied to source bitmaps. One common data compression scheme is JPEG. The JPEG algorithm divides bitmaps into Minimal Coding Units (MCUs), which are rectangular regions of constant size, otherwise known as source tiles.

Each source tile is coded or compressed independently of other source tiles and can also be decompressed independently of the other source tiles. When rendering compressed DL bitmaps, it is inefficient to decompress and cache the entire compressed bitmap.

Efficient caching of decompressed bitmap data is thus a significant issue in low memory rendering systems.

Each DL bitmap has one or more associated affine transforms that describe the transformation from source pixel space to output pixel space. The general form of an affine transform is given by the following equation: 618892 1 -2- O Eqn. 1 Sy B D v where: defines the location ofa pixel in the source pixel space; Sdefines the location of a the ransfored pixel in the output pixel space;

C']

s defines the bitmap translation in the output pixel space; and

AC

S is the transformation matrix.

B D The following equation is used during output tile rendering to determine the source bitmap pixel required to render any given output pixel: [a c x-s Eqn. 2 v b d y-t where: S is the inverse of the transformation matrix.

b d Fig. 1 is an illustration of a source bitmap 100 which has been upscaled and positioned onto a page to be rendered. The dashed lines in Fig. 1 represent tile boundaries within the given output pixel space. In the example of Fig. 1, output tiles have dimensions (in pixels) equal to the dimensions of source tiles, but because of the upscaling, the source tiles appear larger than the output tiles. As shown in Fig. 1, output tiles between the scanlines 110 and 120 intersect with the source bitmap comprising source tiles 130, 140, 150 and 160. In particular, output tile 170 intersects source tiles 130, 140, 150 and 160. Each of these source tiles needs to be available to the rendering 618892 1 -3- C system in order to render output tile 170. When the rendering process moves to the next output tile, a different set of source tiles is needed.

SFetching and decompressing bitmap data and placing the uncompressed data into a tile cache are costly operations. Hence, the number of times a source tile is decompressed should be minimized during the course of rendering. Ideally, each source tile should be decompressed and stored in the cache only once, without the need to copy zor move cached data. Also, the rendering engine that reads cached pixel data should not ,IC be complicated as a result of source bitmap caching.

NI Summary ,IC The present specification relates to a source tile memory cache that is substantially smaller than the size of an uncompressed source bitmap. For the row sequential or column sequential tile-based rendering methods disclosed herein, the run-time behaviour of the source bitmap cache is optimal, as each source tile is fetched, decompressed, and stored in the cache only once. Furthermore, by judicious cache management, the reading of cached pixel values is kept simple, while keeping overall cache size to a minimum.

An aspect of the present invention provides a method for applying a transformation to a source image to generate an output image. Each of the images comprises a plurality of tiles. The method comprises the steps, for a current output tile in output tile order, of: fetching a current source tile immediately following the previously fetched tile in a fetching order dependent on the transformation and the output tile order; storing the current source tile substantially over the least recently stored source tile in cache memory; and generating a current pixel value in the current output tile. The step of generating a current pixel value in the current output tile comprises the sub-steps of: determining, using the transformation, a source pixel location whose corresponding source pixel value contributes to the current pixel value; reading from the cache, the source pixel value corresponding to the determined source pixel location; and generating the current pixel value using the read source pixel value.

Other aspects of the present invention provide a computer system and a computer program product for embodying the above method.

618892_1

INO

Brief description of the drawings "1 Fig. 1 is an illustration of an upscaled source bitmap; SFig. 2a illustrates mapping of source bitmap tiles to output tiles; Fig. 2b shows the memory layout of a source bitmap tile cache according to a Sfirst embodiment of the present invention; Fig. 2e shows reconfiguration of the source bitmap tile cache of Fig. 2b; Fig. 3a is a second illustration of mapping of source bitmap tiles to output tiles; SFig. 3b shows the memory layout of a source bitmap tile cache according to a S 10 second embodiment of the present invention;

INO

SFig. 3e and 3d show reconfiguration of the source bitmap tile cache of Fig. 3b; 7 Fig. 4a illustrates rendering of a skewed bitmap using row sequential output tile rendering; Fig. 4b illustrates rendering of a skewed bitmap using column sequential output tile rendering; Figs. 5a to 5e show a progression of cache usage according to the first embodiment of Fig. 2b; Fig. 6 shows the result of applying a scaling operation to a source bitmap; Fig. 7 shows a pixel grid of the scaled source bitmap of Fig. 6; Fig. 8 illustrates the use of look-up tables to upscale a source bitmap with reference to the pixel grid of Fig. 7; Fig. 9 illustrates the use of look-up tables to upscale and rotate a source bitmap by 90 degrees with reference to the pixel grid of Fig. 7; Fig. 10 is a flowchart of a method for applying a transformation to a source image to generate an output image in accordance with an embodiment of the present invention; and Fig. 11 is a schematic block diagram of a computer system with which embodiments of the present invention may be practised.

Detailed description In the embodiments described hereinafter, source bitmaps within an input display list are decomposed into tiles, where all the tiles have the same pixel dimensions. Also, each source bitmap has an associated affine transform.

618892 1

\O

In the embodiments described hereinafter, the output tiles are rendered in a row Ssequential or column sequential manner. Also, each output tile is rendered to completion

U

Sbefore the rendering of the next tile in the row or column commences.

In the embodiments described hereinafter, the affine transform/s must be such Sthat, for row sequential or column sequential output tile rendering, source tiles can be fetched in either a row sequential or column sequential manner. More specifically, the bitmap tile caching methods according to the embodiments of the present invention are C generally only applicable to affine transforms where at least one, and at most two, of the C 10 coefficients a, b, c and d in Eqn. 2. is/are equal to zero. This means that at least one of Sthe pixel coordinates u and v in the source pixel space remains constant as the renderer Straverses either the x (horizontal) or y (vertical) axis in the output pixel space. The applicable transforms of this type are given below in cases 1 to 6 (the translation terms in Eqn. 1 and Eqn. 2 are ignored here): 1) a 0 and b, c, d From Eqn. 2, u c y and v b x d y. If the output pixel coordinate x is varied while keeping the output pixel coordinate y constant, the input pixel coordinate u will remain constant while the input pixel coordinate v varies. Hence, if the output is rendered in a row sequential manner, then the input bitmap will be read in a column sequential manner. However, if the output pixel coordinate y is varied while keeping the output pixel coordinate x constant, both the input pixel coordinates u and v will vary. Hence, embodiments of the present invention are not applicable if the output is rendered in a column sequential manner when only the coefficient a in Eqn.

2 is equal to zero the coefficients b, c and d are non-zero).

2) b 0 and a, c, d 00: From Eqn. 2, u a x c y and v d y. If the output pixel coordinate x is varied while keeping the output pixel coordinate y constant, the input pixel coordinate v will remain constant while the input pixel coordinate u varies. Hence, if the output is rendered in a row sequential manner, then the input bitmap will be read in a row sequential manner. However, if the output pixel coordinate y is varied while keeping the output pixel coordinate x constant, both the input pixel coordinates u and v will vary. Hence, embodiments of the present invention are not applicable if the output is 618892 1 rendered in a column sequential manner when only the coefficient b in Eqn.

2 is equal to zero the coefficients a, c and d are non-zero).

U

S3) c O and a, b, d From Eqn. 2, u a x and v b x d y. If the output pixel coordinate I y is varied while keeping the output pixel coordinate x constant, the input pixel coordinate u will remain constant while the input pixel coordinate v varies. Hence, if the output is rendered in a column sequential manner, then N, the input bitmap will be read in a column sequential manner. However, if N 10 the output pixel coordinate x is varied while keeping the output pixel coordinate y constant, both the input pixel coordinates u and v will vary.

Hence, embodiments of the present invention are not applicable if the output is rendered in a row sequential manner when only the coefficient c in Eqn. 2 is equal to zero the coefficients a, b and d are non-zero).

4) d= 0 anda, b,c 0: From Eqn. 2, u a x c y and v b x. If the output pixel coordinate y is varied while keeping the output pixel coordinate x constant, the input pixel coordinate v will remain constant while the input pixel coordinate u varies. Hence, if the output is rendered in a column sequential manner, then the input bitmap will be read in a row sequential manner. However, if the output pixel coordinate x is varied while keeping the output pixel coordinate y constant, both the input pixel coordinates u and v will vary. Hence, embodiments of the present invention are not applicable if the output is rendered in a row sequential manner when only the coefficient d in Eqn. 2 is equal to zero the coefficients a, b and c are non-zero).

a,d= 0 andb, c 00: From Eqn. 2, u c y and v b x. If the output pixel coordinate x is varied while keeping the output pixel coordinate y constant, the input pixel coordinate u will remain constant while the input pixel coordinate v varies.

Hence, if the output is rendered in a row sequential manner, then the input bitmap will be read in a column sequential manner. Alternatively, if the output pixel coordinate y is varied while keeping the output pixel coordinate x constant, the input pixel coordinate v will remain constant while the input pixel coordinate u varies. Hence, if the output is rendered in a column 618892 1 O sequential manner, then the input bitmap will be read in a row sequential manner.

S6) b, c 0 and a, d O: From Eqn. 2, u a *x and v d If the output pixel coordinate x is varied while keeping the output pixel coordinate y constant, the input pixel coordinate u varies while the input pixel coordinate v remains constant.

Hence, if the output is rendered in a row sequential manner, then the input bitmap will be read in a row sequential manner. Alternatively, if the output S 10 pixel coordinate y is varied while keeping the output pixel coordinate x Sconstant, the input pixel coordinate v varies while the input pixel coordinate Cu remains constant. Hence, if the output is rendered in a column sequential manner, then the input bitmap will be read in a column sequential manner.

A first embodiment of the present invention will now be described with reference to Figs. 2a to 2c. This embodiment assumes row sequential order generation of output tiles using a source bitmap whose inverse affine transform has matrix coefficients b and c from Eqn. 2 both set to 0 (case 6 above). The matrix coefficients a and d are between 0 and 1. This represents an upscaling of the source bitmap without rotation or skewing. In this case, the rendering of a single output tile requires up to four source tiles.

Fig. 2a shows the mapping of an exemplary source bitmap 200, with source tiles marked tO, tl through to tOO, to the output tiles with dashed boundaries. In this example there are four source tiles per source bitmap row, and each tile is ten pixels square.

Consider first the process of generating the strip of output tiles between scanline 201 and scanline 202. From the indicated output tiles belonging to this strip, tile 210 is rendered first, followed by tile 215 and then tile 220. Once the strip of tiles between scanlines 201 and 202 is rendered, the next strip of tiles between scanlines 202 and 203 is rendered. Of the indicated output tiles belonging to this strip, tile 225 is rendered first, followed by tile 230 and then tile 235.

When rendering output tile 210, source tiles tO and tl need to be present in the cache. When rendering tile 215, however, only source tile tl needs to be available.

Although source tile tO could be discarded on rendering output tile 215, this would require source tile tO to be fetched, decompressed and cached again (later), prior to rendering output tile 225. So, instead of discarding source tile tO, source tile tO is kept in the cache at this stage.

618892 1

INO

Moving next to output tile 220, it can be seen that source tile t2 needs to be available in the cache and so must be fetched and decompressed. Source tiles tO and tl Sare retained at this point.

Prior to rendering tile 225 in the next row of output tiles, the cache contains source tiles tO, tl, t2, t3, and t4. Source tile t5 is then fetched, decompressed, and stored in the cache so that output tile 225 can be rendered. Before rendering output tile 230, the source tile tO least recently stored in the cache can be 'discarded' from the cache, as all output tiles intersecting it have been rendered.

I 10 Moving on to rendering output tile 235, it can be seen that source tile tOO needs

INO

Sto be decompressed and stored in the cache. Because source tile tO has been 'discarded', source tile tOO is decompressed and stored substantially in the memory previously occupied by source tile tO.

With the process of rendering bitmap 200 performed as outlined, a maximum of six source tiles must be kept cached at any given time. More generally, for rendering a source bitmap with the transform matrix parameters described hereinbefore with reference to case 6, and where source bitmap tiles are fetched in row sequential manner, a row sequential output tile renderer requires a cache buffer big enough to contain a single row of source tiles plus an additional two tiles from the next source tile row.

Memory organization of the source tile cache for bitmap 200 is now described with reference to Figs. 2b and 2c. The cache is organized in pixel row sequential order so as to aid quick access to a source bitmap pixel, given a particular output pixel.

Fig. 2b shows the memory layout of the cache during the rendering of output tiles 225 and 230. For the sake of clarity, only source tiles tO, tl, and t5 are shown. The pixels in each row of the cache are stored in pixel row sequential order, with a row step equal to 60 pixels (the number of source tiles per row plus two, multiplied by the tile width). Source tiles t2, t3, and t4 are distributed between source tiles tl and t5 so that source tiles tO, tl, t2, t3, t4 and t5 form a fragment of the source bitmap in pixel row sequential order.

Fig. 2c depicts the process of cache reconfiguration as source tile tOO is decompressed and stored in the cache. This occurs just prior to output tile 235 being rendered.

Referring to Figs. 2b and 2c, pixel 240 represents the upper left pixel of source tile tO. During the rendering of output tiles 225 and 230, the memory address of pixel 240 is the base address (BASE) of cached source tile data. Pixel 270 represents the upper right 618892 1 -9- O pixel of source tile tO. Because the source tile width is 10 pixels, pixel 270 is at memory address BASE 9. Pixel 245, which is the upper left pixel of source tile t5, is at memory address BASE 50. Pixel 260, which represents the leftmost pixel of the second row of pixels in source tile tO, is at memory address BASE 60. Because the source tile height is 10 pixels, pixel 275, which represents the lower right pixel of source tile tO, is at memory address BASE 549. Pixel 285, which represents the lower right pixel of source tile t5 and is the last pixel in the cache, is at memory address BASE 599. The total .IC memory occupied by the cached tiles is 600 pixels.

.I 10 During rendering of output tiles 225 and 230, and with the cache memory layout Sas described, the rendering engine can easily read, or access, any source pixel by storing two memory addresses: BASE0 and BASEl. If the source pixel belongs to tile tO or tl or t2, the pixel can be accessed from memory address BASEO. Otherwise, the source pixel belongs to tile t3 or t4 or t5, and the pixel can be accessed from memory address BASEL.

Let BASEO BASE and BASEl BASE 40 the source tile width multiplied by the number of source tiles per row). Accessing a source pixel from an output pixel given a source bitmap tile width w and height h pixels, can be performed as follows: calculate the source position in the bitmap space corresponding to the position in the output space using equation 2, let u u tOx and v v tOy; where tOx is the column number of pixel 240 in the bitmap and tOy is the row number of pixel 240 in the bitmap, thus translating the origin of the coordinate system to pixel 240, if v h then access the source pixel from tiles t0-t2 at address [BASEO+v*rowstep+u] in the cache, otherwise access the source pixel from tiles t3-t5 at address [BASEI+(vh)*rowstep+u] in the cache.

When source tile tOO is decompressed and stored in the cache, its upper left pixel 250 is written to memory address BASE 60. Remaining pixels from source tile tOO are written in consecutive rows. Pixel 250 is written to the memory address formerly occupied by pixel 260. Pixels in all but the last row of source tile tOO occupy the same memory that 'discarded' source tile tO formerly occupied. In other words, pixels 260 through 275 of source tile tO data are overwritten with source tile tOO data.

As indicated in Fig. 2c, the last row of 10 pixels, i.e. pixels 280 through 265 from source tile tOO, does not overwrite source tile tO data. These pixels occupy memory 618892 1 addresses BASE 600 through BASE 609, outside of the memory range of the cache defined by source tiles tO to t5. Instead of increasing the size of the cache by 10 pixels Seach time a new source tile is decompressed and stored in cache, the cache is allocated sufficient memory to accommodate each newly decompressed source tile in the manner illustrated in Fig. 2c.

Figs. 5a to 5e show a progression of source tile cache usage for a source bitmap comprising sixteen tiles arranged in four rows of four tiles each. Each of Figs. 5a to Fig.

S 10 5e show the source tiles which are active in the source tile cache at different times in the Srendering process. The start of the memory where the cache resides is marked START.

The two addresses in the cache required by the rendering engine are marked BASEO and

BASEL.

Fig. 5a shows the state of the cache when the first six source tiles tO to t5 have been decompressed and stored in the cache. The memory address BASEO points to the upper left pixel of source tile tO (START), and the memory address BASEI points to the upper left pixel of source tile t4 (the tile in the second row of tiles immediately below source tile tO).

Fig. 5b shows the state of the cache on decompressing source tile t6 and storing the uncompressed tile in the cache. The memory address BASE0 has moved to point the upper left pixel of source tile tl and the memory address BASE1 has moved to point to the upper left pixel of source tile Fig. 5e shows the state of the cache on decompressing source tile t7 and storing the uncompressed tile in the cache. The memory address BASEO has moved to point to the upper left pixel of source tile t2 and the memory 'address BASEl has moved to point to the upper left pixel of source tile t6.

The state of the cache after decompressing source tiles t8 and t9 and storing the uncompressed tiles in the cache is shown in Fig. 5d. The memory address BASEO has moved to point the upper left pixel of source tile t4 and the memory address BASE1 has moved to point the upper left pixel of source tile t8.

Fig. 5e shows the state of the cache when the last source tile t15 has been decompressed and stored in the cache. The memory address BASEO points to the upper left pixel of source tile tl0 and the memory address BASE1 points the upper left pixel of source tile t14. The amount of additional memory the cache needs due to the fact that each source tile t6 to t15, when decompressed and stored in the cache, does not 618892 1 -11completely overwrite the tile it displaces, is defined by the number of memory locations CI between the memory addresses BASE0 and START BASE0 START).

With the cache buffer managed in this manner, and with output tiles rendered in row sequential order, each source tile is decompressed only once. In addition, the C substantial overwriting of previous tiles by new tiles in the manner described enables the same simple access formulae to be used throughout the rendering, while minimising the overall cache size.

(I 10 For a source bitmap having dx tiles per row and dy tiles per column, with tiles of Swidth w and height h pixels, the operation of the source tile cache can be summarized as (i follows: 0 Prior to rendering, memory is allocated for the cache buffer. The total size of the allocated memory is (dx 2) w* h (dr (dy 1) 2) w pixels.

a The first row of source tiles and first two source tiles from the next row of the source bitmap are decompressed and stored in the cache, with a pixel row step ofw (dr 2) pixels.

N Each subsequent source tile is decompressed and stored in the next location in the cache, w pixels after the start location of the previously decompressed and stored tile, with row step w (dx 2) pixels. There is no need to shift cache data: lines h 2 of the newly decompressed source tile merely replace lines 1 h 1 of the tile to be overwritten.

SSource tile cache memory is freed on rendering the last output tile for the given source bitmap.

A second embodiment of the present invention is now described with reference to Figs. 3a to 3d. In contrast to the first embodiment, the second embodiment renders output tiles in a column sequential manner. Source tiles are also fetched in a column sequential manner. The second embodiment applies to the case where the matrix coefficients b and c in Eqn. 2 are both set to 0 (case 6, hereinbefore). Matrix coefficients a and d in Eqn. 2 are less than 1.

Fig. 3a shows the mapping of an exemplary source bitmap 300, with source tiles marked tl, t2, t3, t4, t5 t6, and tl 1, to the output tiles with dashed boundaries. Bitmap 300 has four source tiles per column. Consider first the process of rendering the column of output tiles between column-lines 301 and 302. From the indicated output tiles 618892 1 -12- O belonging to this column, output tile 310 is rendered first, followed by output tile 315, and finally output tile 320. Once the column of tiles between column-lines 301 and 302 is Srendered, the next column of tiles between column-lines 302 and 303 is rendered. Of the indicated output tiles belonging to this column, output tile 325 is rendered first, followed by output tile 330, and finally, output tile 340.

When rendering output tile 310, source tiles tl and t2 need to be present in the cache. When rendering output tile 315, however, only source tile t2 needs to be available.

Although source tile tl could be discarded on rendering output tile 315, this would require ,I 10 source tile tl to be decompressed and stored in the cache a second time, prior to rendering Soutput tile 325. So, instead of discarding source tile tl, source tile tl is retained in the cache.

Moving next to output tile 320, it can be seen that source tile t3 needs to be available and must thus be decompressed and stored in the cache. Source tiles tl and t2 are retained in the cache.

Prior to rendering output tile 325 in the next column of output tiles, the cache contains source tiles tl, t2, t3, t4, and t5. Source tile t6 is then decompressed and stored in the cache so that output tile 325 can be rendered. Before rendering output tile 330, source tile tl can be 'discarded' from the cache, as all output tiles intersecting source tile tl have been rendered.

Next, upon rendering output tile 340, it can be seen that source tile tl 1 needs to be decompressed and stored in the cache. As source tile tl has been 'discarded', source tile tI 1 is decompressed and stored in the memory previously occupied by source tile tl.

With the process of rendering bitmap 300 performed as outlined with reference to Fig. 3a, a maximum of six source tiles must be kept in the cache at any given time.

More generally, upon rendering a source bitmap with the transform matrix coefficients described hereinbefore, and where source tiles are fetched in a column sequential manner, a column sequential output tile renderer requires a cache buffer big enough to contain a single column of source tiles plus an additional two source tiles from the next source tile column.

Memory organization of the source tile cache for bitmap 300 is now described with reference to Figs. 3b to 3d. The cache is organized in pixel row sequential order so as to aid quick access to a source bitmap pixel given any output pixel.

Fig. 3b shows the memory layout of the cache during the rendering of output tiles 325 and 330.

618892 1 -13- Fig. 3c depicts the process of cache reconfiguration as source tile t ll is r decompressed and stored in the cache. This occurs just prior to the rendering of output Stile 340.

Pixel 360 represents the upper left pixel of source tile tl. During rendering of r output tiles 325 and 330, the memory address of pixel 360 is the base address (BASE) of cached source tile data.

Pixel 350 represents the upper left comer of source tile t5. As with the source r tile cache depicted in Fig. 2b, cache memory is organised in a row sequential manner. In N 10 the cache of the second embodiment, however, pixels from a single source tile occupy a contiguous block of memory. The cache row step is equal to the source tile width in i pixels. Given a source tile width of 10 pixels and a height of 10 pixels, the address of pixel 350 is BASE 200 BASE, less twice the size in pixels of a source bitmap tile).

During rendering of output tiles 325 and 330, and with the cache memory layout as described, the rendering engine can readily acquire any source pixel by storing two memory addresses: BASE0 and BASEl. If the source pixel belongs to tile tl or t2 or t3, the pixel can be accessed from memory address BASEO. Otherwise, the source pixel belongs to tile t4 or t5 or t6, and the pixel can be accessed from memory address BASEl.

Let BASEO BASE and BASEl BASE- 200. Accessing a source pixel from an output pixel given a source bitmap tile width w and height h pixels, can be performed as follows: calculate the source position in the bitmap space corresponding to the position in the output space using equation 2, let u u tOx and v v tOy; where tOx is the column number of pixel 360 in the bitmap and tOy is the row number of pixel 360 in the bitmap, thus translating the origin of the coordinate system to pixel 360, if u w then access the source pixel from tiles tl-t3 at address [BASEO+v*rowstep+u] in the cache (note that rowstep w), otherwise access the source pixel from tiles t4-t6 at address [BASEl+v*rowstep+(u-w)] in the cache.

When source tile tl 1 is decompressed and stored in the cache, its upper left pixel 370 is written to the memory previously occupied by pixel 360. Remaining pixels from source tile tl I are written in consecutive rows. Within each row, pixels are written in pixel sequential order with a row step equal to 10 pixels. In this way, source tile tll 1 occupies precisely the memory previously occupied by source tile tl. The base cache 618892 1 -14address pointer (BASE) is then advanced by 100 pixels, to the memory address occupied by pixel 365 (the upper left pixel of source tile t2). Now BASE 200 points to pixel Slocation 355 which is the upper left pixel of source tile t6.

Source tile tl 1 is the last source tile in the column of tiles containing tiles t4 t6.

,IC After all of the output tiles between column-lines 302 and 303 have been rendered, the cache memory block holding source tiles t4, t5, t6 and tl 1 is shifted forward by 200 pixels, to the memory region previously occupied by source tiles t6, tl 1, t2 and t3, and the NI base cache pointer (BASE) is set to pixel location 355 which is now the upper left pixel of ,I 10 tile t4, as shown in Fig. 3d. This shifting process obliterates redundant source tiles t2 and t3. The first source tile from the new column of tiles will be decompressed into the beginning of the cache which is at address BASE-200.

With the cache buffer managed in this manner, and the rendering of output tiles in column sequential order, each source tile is decompressed only once. In addition, the complete overwriting of previous tiles by new tiles, and the periodic shifting forward of cached data, in the manner described enables the same simple access formulae to be used throughout the rendering, while minimising the overall cache size.

For a source bitmap having dx tiles per row and dy tiles per column, with tiles of width w and height h pixels, the operation of the source tile cache can be summarized as follows: Prior to rendering, memory is allocated for the cache buffer. The total size of the allocated memory is (dy 2)*w*h pixels. The source allocation address is saved to the variable SOURCE.

m The first column of source tiles is decompressed and stored in the cache, starting at address SOURCE 2 w h, and with row step w pixels.

0 The first two source tiles from the second column in the source bitmap are decompressed and stored in the cache, starting at cache memory address SOURCE, and with row step w pixels.

Each subsequent source tile is decompressed and stored in the next location in the cache, starting at memory address SOURCE 2 w h, w h pixels after the start of the previous source tile in the cache. The row step is w.

a When a complete column of tiles has been decompressed and stored in the cache, cache memory between addresses SOURCE and SOURCE dy w h is moved forwards in memory by an amount equal to 2 w h pixels. This 618892 1 obliterates data from the last two tiles of the previous column, and makes Sroom for the next column of tiles, starting at address SOURCE.

Source tile cache memory is freed on rendering the last output tile for the given source bitmap.

In both embodiments of the present invention described hereinbefore, source z tiles are decompressed and stored in the cache once only. An advantage of the first N embodiment over the second is that no copying or shifting of the pixel data in the cache is S 10 required.

The first embodiment of the present invention may be applied to the rendering of Ssource bitmaps where column sequential output tile rendering results in the fetching of source tiles in a row sequential manner. Such occurs in case 5, referred to hereinbefore.

In addition, the second embodiment of the present invention may be applied to the rendering of bitmaps where row sequential output tile rendering results in the reading of source tiles in a column sequential manner. Such also occurs in case 5, referred to hereinbefore.

In the first and second embodiments of the present invention, caching of source bitmap tiles involves decompression of source tiles and subsequent storing of the uncompressed source tiles in cache memory as described hereinbefore. Variations of the first and second embodiments may involve retrieving uncompressed or compressed source tiles from a slower memory device such as a hard disk, or from across a network, and storing the uncompressed source tile in cache memory as described hereinbefore.

Also, individual pixels within an output tile may be rendered in any order. Individual pixels within an output tile may, for example, be rendered in a row sequential manner, rendering the top scanline of the tile first, and progressing through to the bottom scanline of the tile. Within each scanline, pixels may be rendered from left to right, or right to left.

Alternatively, individual pixels within an output tile may be rendered in a column sequential manner, rendering the rightmost column of pixels first, and progressing through to the leftmost column of pixels in the tile. Within each column of pixels, pixels may be rendered from top to bottom, or bottom to top.

The first embodiment of the present invention may be applied to the rendering of skewed bitmaps where row sequential or column sequential output tile rendering results in the fetching of source tiles in a row sequential manner. Such occurs in cases 2 and 4, referred to hereinbefore (where c and a respectively are the skew terms). In addition, the 618892 1 -16- O second embodiment of the present invention may be applied to the rendering of skewed bitmaps where row sequential or column sequential output tile rendering results in the Sreading of source tiles in a column sequential manner. Such occurs in cases I and 3, referred to hereinbefore. For such skewed bitmaps, source tile cache fragments of constant size are required to render any given output tile. For such skewed bitmaps, the source tile cache may be required to store more than 2 extra tiles, in addition to the full row or column of source tiles described in the first and second embodiments of the NI present invention. The source tile cache may also be required to store more than a single C 10 row or column of source tile data.

Fig. 4a illustrates the rendering of a skewed bitmap where row sequential output tile rendering results in the reading of source tiles in a row sequential manner (case 2 above). As shown in Fig. 4a, output tile 410 maps to two consecutive rows of source tiles.

Also, output tile 410 maps to a maximum of three consecutive source tiles within a single row of source tiles. Output tile 420 maps to four consecutive source tiles t5, t6, t7, and t8 within a single row of source tiles. Constant source tile fragments of four source tiles plus one complete row of source tiles can be used to render any single output tile for the skew shown in Fig. 4a. The source tile cache described in the first embodiment of the present invention can be used in a row sequential output tile rendering system in this case.

The size of the source tile cache must be augmented by two source tiles.

Fig. 4b illustrates the rendering of a skewed bitmap where column sequential output tile rendering results in the reading of source tiles in a column sequential manner, as in case 3 referred to hereinbefore. As shown in Fig. 4b, output tile 430 maps to three consecutive columns of source tiles. Output tile 430 also maps to a maximum of three consecutive source tiles within a single column of source tiles. Output tile 440 also maps to a maximum of three consecutive source tiles within a single column of source tiles.

Constant source tile fragments of 3 three tiles high and 3 tiles wide can be used to render any single output tile for the skew shown in Fig. 4b. The source tile cache described in the second embodiment of the present invention can be used in a column sequential output tile rendering system in this case. The source tile cache must contain two columns of tile data plus three extra source tiles.

An efficient method of bitmap scaling, rotating and flipping is now described.

Fig. 6 shows the result 610 of applying an upscaling operation to a source bitmap 600. In 618892 1 -17this instance, the source bitmap 600 has a width of 5 pixels and a height of 5 pixels. The source bitmap 600 is scaled by a factor of 2.5 in the x direction and 3.33 in the y direction, that is, the transform matrix of equation 1 is: C1 [A B: D 0b 3 33] c1 The scaled bitmap 610 is also shown in Fig. 6. The scaled bitmap 610 has a width of 13 pixels and a height of 17 pixels.

Fig. 7 shows a pixel grid 700 of the scaled bitmap 610 of Fig. 6. Each pixel location in the pixel grid 700 corresponds to a pixel in the scaled bitmap 610 in Fig. 6 and contains the original image pixel location from which the scaled pixel derives its colour as expressed in (column, row) form. For instance, the scaled pixel 710 at column index 9 and row index 14 derives its colour from the pixel in the source bitmap at column index 3 and row index 4.

From Fig. 7, it can be noted that the sequence of source bitmap column indices is row independent. The sequence of source bitmap column indices for all the rows can be represented as a single look-up table 720 with one entry for each column in the scaled bitmap.

From Fig. 7, it can also be noted that the sequence of source bitmap row indices is column independent. The sequence of source bitmap row indices for all the columns can be represented as single look-up table 730 with one entry for each row in the scaled bitmap.

Fig. 8 demonstrates how the look-up tables 720 and 730 of Fig. 7 can be used to construct the scaled bitmap 800. For any pixel location within the scaled bitmap 800, the source bitmap pixel location can be determined by retrieving the source bitmap column index from the look-up table of source bitmap column indices 720 and by retrieving the source bitmap row index from the look-up table of source bitmap row indices 730. For example, the source bitmap pixel location from which the scaled bitmap pixel 810 at column index 6 and row index 10 derives its colour can be determined by retrieving the source bitmap column index from the table of source bitmap column indices 720 corresponding to the scaled bitmap column index of 6 (namely and the source bitmap 618892 1 -18row index from the table of source bitmap row indices 730 corresponding to the scaled N, bitmap row index of 10 (namely 3).

U

d,)

C)

A similar method can be used to construct 90, 180 and 270 degree rotations of a bitmap. For a 90 or 270 degree rotation, a look-up table of source bitmap column indices corresponding to each row in the rotated bitmap is derived, together with a look-up table zof source bitmap row indices corresponding to each column in the rotated bitmap. An N, example of a 90 degree rotation is shown in Fig. 9. The transform matrix from equation 1 C 10 applied to the source bitmap 600 is as follows: 0 [O .5 o BD 2.5 0 1 0L 0 333] This represents the same scaling transformation referred to hereinbefore with reference to Fig. 6, together with a 90 degree clockwise rotation. A translation is also applied to centre the rotated bitmap. By applying the inverse transform to the rotated bitmap pixel locations in the rotated bitmap pixel grid 900, the look-up table of source bitmap column indices 910 corresponding to each row in the rotated bitmap, and the lookup table of source bitmap row indices 920 corresponding to each column in the rotated bitmap, can be derived. For any pixel location within the rotated bitmap 900, the source bitmap pixel location can be determined by retrieving the source bitmap column index from the look-up table of source bitmap column indices 910 and by retrieving the source bitmap row index from the look-up table of source bitmap row indices 920. For example, the source bitmap pixel location from which the rotated bitmap pixel 930 at column index 6 and row index 6 derives its colour can be determined by retrieving the source bitmap column index from the table of source bitmap column indices 910 corresponding to the rotated bitmap row index of 6 (namely 2) and the source bitmap row index from the table of source bitmap row indices 920 corresponding to the rotated bitmap column index of 6 (namely A similar procedure can be used to apply a 180 and 270 degree rotation of a bitmap.

The method described above also generalises to any affine transform where the transformation matrix is either a diagonal matrix with matrix coefficients B and C equal to zero, or an anti-diagonal matrix with matrix coefficients A and D equal to zero.

618892 1 -19- Fig. 10 is a flowchart of a method for applying a transformation to a source C image to generate an output image in accordance with an embodiment of the present

U

Sinvention. Each of the input and output images comprise a plurality of tiles. The method of Fig. 10 is performed for a current tile according to an output tile order.

C Referring to Fig. 10, at step 1010, a current source tile immediately following the previously fetched tile is fetched in a fetching order dependent on the transformation and the output tile order.

r The current source tile is then stored in a memory cache, at step 1020. The N 10 current source tile may be stored substantially or completely over the source tile least recently stored in the cache.

N A current pixel value in the current output tile is generated at step 1030 by performing the sub-steps of: determining, using the transformation, a source pixel location whose corresponding source pixel value contributes to the current pixel value; (ii) reading from the cache the source pixel value corresponding to the determined source pixel location; and (iii) generating the current pixel value using the read source pixel value.

In embodiments in which the fetching order is row order, the least recently stored source tile may comprise the source tile in the tile row previous to that comprising the current source tile and in the tile column preceding the tile column preceding the tile column comprising the current source tile. In this instance, the reading step may comprise the sub-steps of: determining whether the vertical coordinate of the determined source pixel location is less than or equal to the height of the source tile; (ii) summing, if the determination returns in the affirmative, the product of the vertical coordinate and a row step and the horizontal coordinate of the determined source pixel, and adding the sum to a first base address to obtain the address in the cache of the source pixel value; or (iii) otherwise, summing the product of the vertical coordinate less the height and a row step and the horizontal coordinate of the determined source pixel, and adding the sum to a second base address to obtain the address in the cache of the source pixel value. The first base address may comprise the address in cache memory of the top-left pixel of the least recently stored source tile, and the second base address may comprise the address in the cache memory of the top-left pixel of the source tile in the same column and on the next row of the source image as the least recently stored source tile. The row step may comprise the product of the number of source tiles in a row of the source bitmap image 618892 1 O plus two and the width of the source tile. The current source tile may be stored over all but the first row of the tile least recently stored in the cache memory.

SIn embodiments in which the fetching order is column order, the least recently stored source tile may comprise the source tile in the tile column previous to that C comprising the current source tile and in the tile row preceding the tile row preceding the tile row comprising the current source tile. In this instance, the reading step may comprise the sub-steps of: determining whether the horizontal coordinate of the determined NI source pixel location is less than or equal to the width of the source tile; (ii) summing, if ,I 10 the determination returns in the affirmative, the product of the vertical coordinate and a Srow step and the horizontal coordinate of the determined source pixel, and adding the sum ,IC to a first base address to obtain the address in the cache memory of the source pixel value; or (iii) otherwise, summing the product of the vertical coordinate and a row step and the horizontal coordinate of the determined source pixel less the width, and adding the sum to a second base address to obtain the address in the cache memory of the source pixel value. The first base address may comprise the address in the cache memory of the topleft pixel in the least recently stored source tile in the cache memory, and the second base address may comprise the address in the cache memory of the top-left pixel of the source tile in the same row and on the next column of the source image as the least recently stored source tile. The row step may comprise the width of the source tile. The current source tile may be stored completely over the least recently stored tile in the cache memory.

Methods described herein for applying a transformation to a source image to generate an output image may be implemented using a computer system 1100, such as that shown in Fig. 11. More specifically, the methods described herein with reference to the accompanying drawings may be implemented as software, such as one or more application programs executable within the computer system 1100. In particular, the steps of the methods described herein may be effected by instructions in the software that are carried out within the computer system 1100. The instructions may be formed as one or more code modules, each for performing one or more particular tasks. The software may be stored in a computer readable medium, including the storage devices described hereinafter, for example. The software is loaded into the computer system 1100 from the computer readable medium, and then executed by the computer system 1100. A computer readable medium having such software or computer program recorded on it is a computer 618892 1 -21program product. The use of the computer program product in the computer system 1100 C preferably effects an advantageous apparatus for applying a transformation to a source (1)image to generate an output image in accordance with embodiments of the present invention.

C1 As seen in Fig. 11, the computer system 1100 is formed by a computer module 1101, input devices such as a keyboard 1102 and a mouse pointer device 1103, and output devices including a printer 1115, a display device 1114 and I loudspeakers 1117. An external Modulator-Demodulator (Modem) transceiver I 10 device 1116 may be used by the computer module 1101 for communicating to and from a communications network 1120 via a connection 1121. The network 1120 may be a widearea network (WAN), such as the Internet or a private WAN. Where the connection 1121 is a telephone line, the modem 1116 may be a traditional "dial-up" modem.

Alternatively, where the connection 1121 is a high capacity (eg: cable) connection, the modem 1116 may be a broadband modem. A wireless modem may also be used for wireless connection to the network 1120.

The computer module 1101 typically includes at least one processor unit 1105, and a memory unit 1106, for example, formed from semiconductor random access memory (RAM) and/or read only memory (ROM). The module 1101 also comprises cache memory, preferably disposed internally to the at least one processor unit 1105, which may be used to store data relating to source tiles in accordance with embodiments of the present invention. The module 1101 also includes a number of input/output (I/O) interfaces including an audio-video interface 1107 that couples to the video display 1114 and loudspeakers 1117, an I/O interface 1113 for the keyboard 1102 and mouse 1103 and optionally a joystick (not illustrated), and an interface 1108 for the external modem 1116 and printer 1115. In some implementations, the modem 1116 may be incorporated within the computer module 1101, for example within the interface 1108. The computer module 1101 also has a local network interface 1111 which, via a connection 1123, permits coupling of the computer system 1100 to a local computer network 1122, known as a Local Area Network (LAN). As also illustrated, the local network 1122 may also couple to the wide network 1120 via a connection 1124, which would typically include a socalled "firewall" device or similar functionality. The interface 1111 may be formed by an EthernetTM circuit card, a wireless BluetoothTM or an IEEE 802.21 wireless arrangement.

The interfaces 1108 and 1113 may afford both serial and parallel connectivity, the former typically being implemented according to the Universal Serial Bus (USB) 618892 1 -22-

INO

0 standards and having corresponding USB connectors (not illustrated). Storage

O

devices 1109 are provided and typically include a hard disk drive (HDD) 1110. Other Sdevices such as a floppy disk drive and a magnetic tape drive (not illustrated) may also be used. An optical disk drive 1112 is typically provided to act as a non-volatile source of data. Portable memory devices, such optical disks (eg: CD-ROM, DVD), USB-RAM, and floppy disks for example may then be used as appropriate sources of data to the system 1100.

C The components 1105 to 1113 of the computer module 1101 typically communicate C 10 via an interconnected bus 1114 and in a manner which results in a conventional mode of O operation of the computer system 1100 known to those in the relevant art. Examples of computers on which the described arrangements can be practised include IBM-PC's and compatibles, Sun Sparcstations, Apple Mac w or similar computer systems evolved therefrom.

Typically, the application programs discussed above are resident on the hard disk drive lll0 and are read and controlled in execution by the processorunit 1105.

Intermediate storage of such programs and any data fetched from the networks 1120 and 1122 may be accomplished using the semiconductor memory 1106, possibly in concert with the hard disk drive 1110. In some instances, the application programs may be supplied to the user encoded on one or more CD-ROM and read via the corresponding drive 1112, or alternatively may be retrieved by the user from the networks 1120 or 1122.

Still further, the software can also be loaded into the computer system 1100 from other computer readable media. Computer readable media refers to any storage medium that participates in providing instructions and/or data to the computer system 1100 for execution and/or processing. Examples of such media include floppy disks, magnetic tape, CD-ROM, a hard disk drive, a ROM or integrated circuit, a magneto-optical disk, or a computer readable card such as a PCMCIA card and the like, whether or not such devices are internal or external of the computer module 1101. Examples of computer readable transmission media that may also participate in the provision of instructions and/or data include radio or infra-red transmission channels as well as a network connection to another computer or networked device, and the Intemrnet or Intranets including e-mail transmissions and information recorded on Websites and the like.

The methods described herein in accordance with embodiments of the present invention may alternatively be implemented in dedicated hardware such as one or more 618892 1 -23- INO integrated circuits. Such dedicated hardware may include graphic processors, digital 0 signal processors, or one or more microprocessors and associated memories.

It is apparent from the foregoing that the arrangements described are applicable to the computer and data processing industries. The foregoing describes only a limited number of embodiments of the present invention, and modifications and/or changes can be made thereto without departing from the scope and spirit of the invention, the C, embodiments being illustrative and not restrictive.

n Io In the context of this specification, the word "comprising" means "including Sprincipally but not necessarily solely" or "having" or "including", and not "consisting only of'. Variations of the word "comprising", such as "comprise" and "comprises" have correspondingly varied meanings.

618892 1

Claims (14)

1. A method of applying a transformation to a source image to generate an output image, each said image comprising a plurality of tiles, said method comprising the N steps, for a current output tile in output tile order, of: fetching a current source tile immediately following the previously fetched tile in za fetching order dependent on said transformation and said output tile order; N storing said current source tile in a cache substantially over the least recently Vt) N 10 stored source tile in said cache; and Sgenerating a current pixel value in said current output tile by the steps of: determining, using said transformation, a source pixel location whose corresponding source pixel value contributes to said current pixel value; reading from said cache the source pixel value corresponding to said determined source pixel location; and generating said current pixel value using the read source pixel value.

2. The method according to claim 1, wherein said fetching order is row order, and said least recently stored source tile is the source tile in the tile row previous to that comprising said current source tile and in the tile column preceding the tile column preceding the tile column comprising said current source tile.

3. The method according to claim 2, wherein said reading step comprises the sub-steps of: determining whether the vertical coordinate of said determined source pixel location is less than or equal to the height of said source tile, summing, if said determination returns in the affirmative, the product of said vertical coordinate and a row step and the horizontal coordinate of said determined source pixel, and adding the sum to a first base address to obtain the address in said cache of said source pixel value; otherwise summing the product of said vertical coordinate less said height and a row step and the horizontal coordinate of said determined source pixel, and adding the sum to a second base address to obtain the address in said cache of said source pixel value. 618892 1

4. The method according to claim 3 wherein said first base address is the address in said cache of the top-left pixel in the least recently stored source tile in said cache, and said second base address is the address in said cache of the top-left pixel of the source tile in the same column and on the next row of said source image as said least C recently stored source tile. The method according to claim 3, wherein said row step is the product (N of: (N 10 the number of source tiles in a row of said source bitmap image plus two, and the width of said source tile.

6. The method according to claim 2, wherein said current source tile is stored over all but the first row of said least recently stored tile in said cache.

7. The method according to claim 1, wherein said fetching order is column order, and said least recently stored source tile is the source tile in the tile column previous to that comprising said current source tile and in the tile row preceding the tile row preceding the tile row comprising said current source tile.

8. The method according to claim 7, wherein said reading step comprises the sub-steps of: determining whether the horizontal coordinate of said determined source pixel location is less than or equal to the width of said source tile, summing, if said determination returns in the affirmative, the product of the vertical coordinate and a row step and the horizontal coordinate of said determined source pixel, and adding the sum to a first base address to obtain the address in said cache of said source pixel value; otherwise summing the product of said vertical coordinate and a row step and the horizontal coordinate of said determined source pixel less said width, and adding the sum to a second base address to obtain the address in said cache of said source pixel value.

9. The method according to claim 8 wherein said first base address is the address in said cache of the top-left pixel in the least recently stored source tile in said cache, and said second base address is the address in said cache of the top-left pixel of the 618892 1 -26- source tile in the same row and on the next column of said source image as said least recently stored source tile. C)

10. The method according to claim 8, wherein said row step is the width of N, said source tile.

11. The method according to claim 7, wherein said current source tile is C stored completely over said least recently stored tile in said cache. C

12. A computer system for applying a transformation to a source image to generate an output image, each said image comprising a plurality of tiles, said computer system comprising at least one processing unit, a memory unit coupled to said at least one processing unit and a cache memory coupled to said at least one processing unit, wherein said at least one processing unit is programmed, for a current output tile in output tile order, to: fetch, from said memory unit, a current source tile immediately following the previously fetched tile in a fetching order dependent on said transformation and said output tile order; store said current source tile in said cache substantially over the source tile least recently stored in said cache; and generate a current pixel value in said current output tile by: determining, using said transformation, a source pixel location whose corresponding source pixel value contributes to said current pixel value; reading from said cache the source pixel value corresponding to said determined source pixel location; and generating said current pixel value using the read source pixel value.

13. The computer system according to claim 12, wherein said fetching order is row order, and said least recently stored source tile is the source tile in the tile row previous to that comprising said current source tile and in the tile column preceding the tile column preceding the tile column comprising said current source tile.

14. The computer system according to claim 12, wherein said fetching order is column order, and said least recently stored source tile is the source tile in the tile 618892 1

27- Ccolumn previous to that comprising said current source tile and in the tile row preceding O C, the tile row preceding the tile row comprising said current source tile. 15. A computer program product comprising a computer readable medium comprising a computer program recorded therein for applying a transformation to a source image to generate an output image, each said image comprising a plurality of tiles, said computer program product comprising computer software program code for: tfetching a current source tile immediately following the previously fetched tile in IND 10 a fetching order dependent on said transformation and said output tile order; Sstoring said current source tile in a cache substantially over the least recently stored source tile in said cache; and generating a current pixel value in said current output tile by the steps of: determining, using said transformation, a source pixel location whose corresponding source pixel value contributes to said current pixel value; reading from said cache the source pixel value corresponding to said determined source pixel location; and generating said current pixel value using the read source pixel value. 16. The computer program product according to claim 15, wherein said fetching order is row order, and said least recently stored source tile is the source tile in the tile row previous to that comprising said current source tile and in the tile column preceding the tile column preceding the tile column comprising said current source tile. 17. The computer program product according to claim 15, wherein said fetching order is column order, and said least recently stored source tile is the source tile in the tile column previous to that comprising said current source tile and in the tile row preceding the tile row preceding the tile row comprising said current source tile. 18. A method of applying a transformation to a source image to generate an output image, said method substantially as herein described with reference to an embodiment as shown in one or more of the accompanying drawings. 618892 1 -28- I 19. A computer system for applying a transformation to a source image to C generate an output image, said computer system substantially as herein described with Sreference to an embodiment as shown in one or more of the accompanying drawings. 20. A computer program product for applying a transformation to a source image to generate an output image, said computer program product substantially as herein described with reference to an embodiment as shown in one or more of the accompanying drawings. SDated 22 December, 2006 SCanon Kabushiki Kaisha Patent Attorneys for the Applicant/Nominated Person SPRUSON FERGUSON 618892 1