AU2003251718A1 - Formation of lattice-tuning semiconductor substrates - Google Patents

Formation of lattice-tuning semiconductor substrates

Info

Publication number
AU2003251718A1
AU2003251718A1 AU2003251718A AU2003251718A AU2003251718A1 AU 2003251718 A1 AU2003251718 A1 AU 2003251718A1 AU 2003251718 A AU2003251718 A AU 2003251718A AU 2003251718 A AU2003251718 A AU 2003251718A AU 2003251718 A1 AU2003251718 A1 AU 2003251718A1
Authority
AU
Australia
Prior art keywords
lattice
formation
semiconductor substrates
tuning semiconductor
tuning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003251718A
Inventor
Adam Daniel Capewell
Timothy John Grasby
Evan Hubert Cresswell Parker
Terence Whall
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Warwick
Original Assignee
University of Warwick
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Warwick filed Critical University of Warwick
Publication of AU2003251718A1 publication Critical patent/AU2003251718A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02Epitaxial-layer growth
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10Inorganic compounds or compositions
    • C30B29/52Alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02441Group 14 semiconducting materials
    • H01L21/0245Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02505Layer structure consisting of more than two layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/0251Graded layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
AU2003251718A 2002-05-31 2003-05-30 Formation of lattice-tuning semiconductor substrates Abandoned AU2003251718A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GBGB0212616.7A GB0212616D0 (en) 2002-05-31 2002-05-31 Formation of lattice-tuning semiconductor substrates
GB0212616.7 2002-05-31
PCT/EP2003/050207 WO2003103031A2 (en) 2002-05-31 2003-05-30 Formation of lattice-tuning semiconductor substrates

Publications (1)

Publication Number Publication Date
AU2003251718A1 true AU2003251718A1 (en) 2003-12-19

Family

ID=9937802

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003251718A Abandoned AU2003251718A1 (en) 2002-05-31 2003-05-30 Formation of lattice-tuning semiconductor substrates

Country Status (8)

Country Link
US (1) US7214598B2 (en)
EP (1) EP1509949B1 (en)
JP (1) JP2005528795A (en)
KR (1) KR20050013563A (en)
CN (1) CN100437905C (en)
AU (1) AU2003251718A1 (en)
GB (1) GB0212616D0 (en)
WO (1) WO2003103031A2 (en)

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DE102004021578A1 (en) 2003-09-17 2005-04-21 Aixtron Ag Method and apparatus for depositing mono- or multi-component layers and layer sequences using non-continuous injection of liquid and dissolved starting substances via a multi-channel injection unit
US20050132952A1 (en) * 2003-12-17 2005-06-23 Michael Ward Semiconductor alloy with low surface roughness, and method of making the same
US7247583B2 (en) 2004-01-30 2007-07-24 Toshiba Ceramics Co., Ltd. Manufacturing method for strained silicon wafer
GB2411047B (en) * 2004-02-13 2008-01-02 Iqe Silicon Compounds Ltd Compound semiconductor device and method of producing the same
US7118995B2 (en) 2004-05-19 2006-10-10 International Business Machines Corporation Yield improvement in silicon-germanium epitaxial growth
JP2008506617A (en) * 2004-07-15 2008-03-06 アイクストロン、アーゲー Method for depositing a film containing Si and Ge
US7682952B2 (en) 2004-11-30 2010-03-23 Massachusetts Institute Of Technology Method for forming low defect density alloy graded layers and structure containing such layers
EP1705697A1 (en) * 2005-03-21 2006-09-27 S.O.I. Tec Silicon on Insulator Technologies S.A. Composition graded layer structure and method for forming the same
JP2007036134A (en) * 2005-07-29 2007-02-08 Toshiba Corp Semiconductor wafer and method for manufacturing semiconductor device
US7902046B2 (en) * 2005-09-19 2011-03-08 The Board Of Trustees Of The Leland Stanford Junior University Thin buffer layers for SiGe growth on mismatched substrates
WO2007053686A2 (en) 2005-11-01 2007-05-10 Massachusetts Institute Of Technology Monolithically integrated semiconductor materials and devices
US20070154637A1 (en) * 2005-12-19 2007-07-05 Rohm And Haas Electronic Materials Llc Organometallic composition
US8063397B2 (en) 2006-06-28 2011-11-22 Massachusetts Institute Of Technology Semiconductor light-emitting structure and graded-composition substrate providing yellow-green light emission
US8115195B2 (en) 2008-03-20 2012-02-14 Siltronic Ag Semiconductor wafer with a heteroepitaxial layer and a method for producing the wafer
US20090242989A1 (en) * 2008-03-25 2009-10-01 Chan Kevin K Complementary metal-oxide-semiconductor device with embedded stressor
US8084788B2 (en) * 2008-10-10 2011-12-27 International Business Machines Corporation Method of forming source and drain of a field-effect-transistor and structure thereof
KR20100064742A (en) * 2008-12-05 2010-06-15 한국전자통신연구원 Growth of pure ge layer with low threadin dislocation density
US7902009B2 (en) * 2008-12-11 2011-03-08 Intel Corporation Graded high germanium compound films for strained semiconductor devices
US20110070746A1 (en) * 2009-09-24 2011-03-24 Te-Yin Kao Method of increasing operation speed and saturated current of semiconductor device and method of reducing site flatness and roughness of surface of semiconductor wafer
GB2519338A (en) * 2013-10-17 2015-04-22 Nanogan Ltd Crack-free gallium nitride materials
KR102259328B1 (en) 2014-10-10 2021-06-02 삼성전자주식회사 Semiconductor device and method for fabricating the same
US9842900B2 (en) 2016-03-30 2017-12-12 International Business Machines Corporation Graded buffer layers with lattice matched epitaxial oxide interlayers
US10801895B2 (en) 2017-09-07 2020-10-13 Teledyne Scientific & Imaging, Llc Spectroscopic focal plane array and method of making same
CN109950153B (en) * 2019-03-08 2022-03-04 中国科学院微电子研究所 Semiconductor structure and manufacturing method thereof
CN109920738A (en) * 2019-03-08 2019-06-21 中国科学院微电子研究所 Semiconductor structure and its production method
CN109887847A (en) * 2019-03-08 2019-06-14 中国科学院微电子研究所 Semiconductor structure and its production method

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5256550A (en) * 1988-11-29 1993-10-26 Hewlett-Packard Company Fabricating a semiconductor device with strained Si1-x Gex layer
US5221413A (en) 1991-04-24 1993-06-22 At&T Bell Laboratories Method for making low defect density semiconductor heterostructure and devices made thereby
US5442205A (en) * 1991-04-24 1995-08-15 At&T Corp. Semiconductor heterostructure devices with strained semiconductor layers
US5461243A (en) * 1993-10-29 1995-10-24 International Business Machines Corporation Substrate for tensilely strained semiconductor
US5891769A (en) * 1997-04-07 1999-04-06 Motorola, Inc. Method for forming a semiconductor device having a heteroepitaxial layer
US6107653A (en) * 1997-06-24 2000-08-22 Massachusetts Institute Of Technology Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization
DE19859429A1 (en) * 1998-12-22 2000-06-29 Daimler Chrysler Ag Process for the production of epitaxial silicon germanium layers
JP2003517726A (en) 1999-09-20 2003-05-27 アンバーウェーブ システムズ コーポレイション Fabrication method of relaxed silicon germanium layer
EP1249036A1 (en) * 2000-01-20 2002-10-16 Amberwave Systems Corporation Low threading dislocation density relaxed mismatched epilayers without high temperature growth
JP4269541B2 (en) * 2000-08-01 2009-05-27 株式会社Sumco Semiconductor substrate, field effect transistor, method of forming SiGe layer, method of forming strained Si layer using the same, and method of manufacturing field effect transistor

Also Published As

Publication number Publication date
US7214598B2 (en) 2007-05-08
WO2003103031A3 (en) 2004-04-08
EP1509949A2 (en) 2005-03-02
EP1509949B1 (en) 2012-08-22
WO2003103031A2 (en) 2003-12-11
JP2005528795A (en) 2005-09-22
CN100437905C (en) 2008-11-26
CN1656603A (en) 2005-08-17
GB0212616D0 (en) 2002-07-10
KR20050013563A (en) 2005-02-04
US20050239255A1 (en) 2005-10-27

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