AU2003250618B2

AU2003250618B2 - An identification device and identification system

Info

Publication number: AU2003250618B2
Application number: AU2003250618A
Authority: AU
Inventors: Stuart Colin Littlechild; Graham Alexander Munro Murdoch
Original assignee: Sato Holdings Corp
Current assignee: Sato Holdings Corp
Priority date: 2002-08-22
Filing date: 2003-08-22
Publication date: 2009-11-19
Anticipated expiration: 2023-08-22
Also published as: AU2003250618A1; AU2006203161A1; AU2009251121A1

Description

WO 2004/019055 PCT/AU2003/001072 AN IDENTIFICATION DEVICE AND IDENTICATION SYSTEM FIELD OF INVENTION The present invention relates to an identification device, and system incorporating such. The invention has been developed primarily as a radio frequency identification ("RFID") 5 tag for a parcel, document, or postal handling system and will be described hereinafter with reference to these applications. However, the invention is not limited to those particular fields of use and is also suitable to inventory management, stock control systems, and other applications. BACKGROUND Passive RFID tags are known, and generally include a resonant tuned antenna coil 10 electrically connected to an integrated circuit (IC). Examples of such RFID tags include: US 5,517,194 (Carroll et al); US 4,546,241 (Walton); US 5,550,536 (Flaxel); and US 5,153,583 (Murdoch). Systems that employ RFID typically include an interrogator that generates a magnetic field at the resonant frequency of the tuned antenna coil. When the coil is located within the 15 magnetic field, the two couple and a voltage is generated in the coil. The voltage in the coil is magnified by the coil's Q factor and provides electrical power to the IC. With this power, the IC is thereby able to generate a coded identification signal that is ultimately transmitted to the interrogator. Limitations arise because the resonant current that flows in the tuned antenna coil also 20 generates a magnetic field in the region of the coil. That is, if there is an object - such as a second tag with a second coil - disposed near the first coil, the voltage generated by the first coil (and the second coil as well) will be reduced by the partial cancellation - or even complete cancellation - of these respective fields. In turn, this consequential reduction in power will not allow the first tag (and likely the second tag as well) to reliably provide an identification signal 25 to the interrogator. In this light, many fields that employ such tags - such as baggage handling services, letter carrying services, inventory management systems, etc. - cannot be processed in "dense" configurations. In other words, such articles must be sufficiently spread apart for the tags - and systems incorporating such tags - to operate reliably. Such "density" limitations thus tend to 30 result in speed and efficiency restrictions. The discussion of the prior art within this specification is to assist the addressee understand the invention and is not an admission of the extent of the common general knowledge in the field of the invention.

2 SUMMARY OF THE INVENTION It is an object of the present invention to overcome, or at least substantially ameliorate, one or more of the disadvantages of the prior art or at least to provide a useful alternative. 5 According to a first aspect of the invention there is provided an identification device for receiving a first signal and transmitting a second signal, the device including: a non-resonant receiving means for receiving the first signal and employing the first signal to generate a voltage; 10 wherein the non-resonant receiving means generates a first current from the voltage; an integrated circuit; wherein the integrated circuit includes a state selection means for selecting whether the device is in a first state or a second state; a connection between the non-resonant receiving means and the 15 integrated circuit; a transmission means for generating the second signal; wherein - relative to the second state - a relatively larger amount of the first current flows through the non-resonant receiving means when the device is in the first state; and 20 wherein - relative to the first state - a relatively smaller amount of the first current flows through the non-resonant receiving means when the device is in the second state. According to a second aspect of the invention there is provided a system for identifying articles, the system including: 25 a signal generator for generating a first signal; a plurality of identification devices, each individual device being respectively associated with at least one article; wherein each device includes: a non-resonant receiving means for receiving the first signal and employing the first signal to generate a voltage; 30 wherein the non-resonant receiving means generates a first current from the voltage; an integrated circuit; 3 wherein the integrated circuit includes a state selection means for selecting whether the device is in a first state or a second state; a connection between the non-resonant receiving means and the integrated circuit; 5 a transmission means for generating the second signal; wherein - relative to the second state-a relatively larger amount of the first current flows through the non-resonant receiving means when the device is in the first state; and wherein - relative to the first state-a relatively smaller amount of the first 10 current flows through the non-resonant receiving means when the device is in the second state. According to a third aspect of the invention there is provided a method of interrogating an identification device including the steps of: providing an identification device having an integrated circuit, a non 15 resonant receiving means connected to the integrated circuit and a transmitting means; receiving a first signal within the non-resonant receiving means) and employing the first signal to generate a voltage; generating a first current from the voltage; 20 selecting a first or second state for the identification device, wherein a relatively larger amount of the first current flows through the non-resonant receiving means when the device is in the first state and wherein a relatively smaller amount of the first current flows through the non-resonant receiving means when the device is in the second state such that when the identification 25 device is in the second state it does not interfere with the operation of other identification devices in the first state, According to a fourth aspect of the invention there is provided a method for interrogating an identification device in close proximity to other identification devices including the steps of: 30 providing an identification device having an integrated circuit and a transmitting means; receiving a first signal within the non-resonant receiving means and employing the first signal to generate a voltage; 4 generating a first current from the voltage; randomly or pseudo-randomly selecting a first or second state for the identification device, wherein a relatively larger amount of the first current flows through the non-resonant receiving means when the device is in the first state 5 and wherein a relatively smaller amount of the first current flows through the non resonant receiving means when the device is in the second state. Other aspects and preferred aspects are disclosed in the specification and/or defined in the appended claims, forming a part of the description of the invention. 10 BRIEF DESCRIPTION OF THE DRAWINGS Preferred embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which: Figure 1 is a schematic representation of a device according to a preferred embodiment of the invention; 15 Figure 2 is a symbolic circuit diagram of a typical prior art tag; Figure 3 is a symbolic circuit diagram of an RFID device according to one embodiment of the invention; Figure 4 is a symbolic circuit diagram of another embodiment of the invention that includes a voltage multiplier; 20 Figure 5 is a symbolic circuit diagram of a further embodiment of the invention that includes a voltage doubler circuit; Figure 6 is a symbolic circuit diagram of a further embodiment of the invention that includes both a voltage doubler circuit and a full wave circuit; Figure 7 is a symbolic circuit diagram of a further alternative embodiment 25 of the invention that includes a circuit for changing the current collection efficiency of the antenna; Figure 8 is a symbolic circuit diagram of a further embodiment of the invention where the circuit for changing the current collection efficiency is on the DC side; 30 Figure 9 is a symbolic circuit diagram of another embodiment of the invention that includes a circuit for changing the operating voltage; 4a Figure 10 is a symbolic circuit diagram of a further embodiment of the invention that includes a series voltage regulator circuit; Figure 11 is a circuit model for the prior art circuit of Figure 2; Figure 12 is a circuit model for the device of Figure 13; 5 Figure 13 is a perspective view of a plurality of stacked envelopes, each of which contains a device according to Figure 3; Figure 14 is a plan view of the device of Figure 3; 5 Figure 15 is a perspective cut-away view of a parcel according to another aspect of the invention; Figure 16 is an alternative symbolic embodiment to that of Figure 3, where the antenna coil is substituted with a generic interrogation signal-receiving device; 5 6 5 10 THIS PAGE IS INTENTIONALLY BLANK 15 WO 2004/019055 PCT/AU2003/001072 -7 Figure 17 is an alternative symbolic embodiment to that of Figure 3, where the antenna coil is substituted with a dipole antenna; Figure is an alternative symbolic embodiment to that of Figure 3, where the antenna coil is substituted with a capacitive antenna; and 5 Figure 19 is a schematic representation of a system according to a preferred embodiment of the invention. DETAILED DESCRIPTION OF THE INVENTION Introductory Comments Regarding the Figures' Symbolic Representation It is important to note at the outset that Figures 3 to 11, and 15 to 18 are "symbolic" 10 models of preferred embodiments of the invention, and Figure 2 is "symbolic" of a prior art tag. In contrast, Figure 1 is a schematic representation of the invention. That is, as shown in Figure 1, a preferred embodiment of the invention is comprised of a receiver portion 35; an integrated circuit 37 with one or more functionalities; a connection 39 between the two; and a state selection means 41 that determines whether the device is in a first 15 state or a second state; and a transmission means 45 - preferably in the form of an antenna 47. Again, these components are reflected symbolically in Figures 3 to 11, and 15 to 18. A Fist Embodiment of the Invention A first embodiment of the invention, in the form of a radio frequency identification ("RFID") device or tag 1, is symbolically illustrated in Figure 3. The tag includes a multi-turn 20 coil 3 for receiving an interrogation signal. A transceiver, in the form of an integrated circuit (IC) 4, is connected to the coil 3 and is responsive to the interrogation signal. In other embodiments, other devices are used as the transceiver; such devices will be readily apparent to those skilled in the art. In this embodiment, coil 3 and the circuit 4 are mounted on a common generally rectangular substrate 2. In other preferred embodiments, the IC includes a memory 42. 25 Two "States" Circuit 4 toggles between a first state and a second state, wherein the current drawn from the coil 3 by the circuit 4 - in the presence of the interrogation signal - during a first state is greater than the current drawn during a second state. More specifically, circuit 4 has a current cycle during which the circuit randomly selects either the first or the second state for the 30 duration of the cycle. The random selection of state during the cycle by each individual tag reduces the risk of two adjacent tags simultaneously operating in the first state. Moreover, in this embodiment, the selection of the second state by circuit 4 is about 16 times more probable than the selection of the first state. That is, the probability of the circuit 4 drawing a high current - and thereby jeopardizing the performance of an adjacent tag, and itself, WO 2004/019055 PCT/AU2003/001072 -8 by their mutual coupling is 1/16. Accordingly, the tags may operate at a much smaller spatial separation than could be achieved by prior art tags. The state selection means is implemented with digital circuits. These circuits are designed to select the current state according to the chosen algorithm or method. There are 5 several methods which can be used to implement the state selection circuits. Logic gates can be used to create a dedicated logic circuit for determining the state selection. A state engine consisting of logic arrays can be designed to implement the state selection function. A microcontroller or processor can execute software instructions that code for the chosen algorithm or method. The preferred embodiment is a logic array controlled by a microcontroller. The 10 microcontroller software executes the slower parts of the chosen algorithm or method while the logic array performs the faster parts of the chosen algorithm or method. Dimensions The substrate 2 is about 80 mm by 50 mm, and includes a plurality of layers that are laminated together to encapsulate the coil 3 and the circuit 4. In this embodiment, the thickness 15 of the tag I is about 0.3 mm. In other embodiments, the dimensions of tag I are bigger or smaller. That is, it is generally preferable for the tag to be sized such that it may be unobtrusively incorporated into packaging and other articles. Devices Used to Transmit the Identification Signal In the preferred embodiment, the coil 3 transmits an identification signal generated by 20 the transceiver. In other embodiments, a second separate antenna coil is used to transmit the identification signal. Devices Used to Receive the Interrogation Si2nal While in this embodiment, the antenna is the coil 3, other devices may be employed to receive the interrogation signal. Examples of such alternative devices are shown in Figures 16, 25 17 and 18. In Figure 16, the interrogation signal is received by a non-specific or generic receiving device 31. As shown in Figure 17 includes a dipole antenna 32 is used for receiving a radiated interrogation signal. In other embodiments (not shown), device 31 is a monopole. In still further embodiments, such as that illustrated in Figure 18, device 31 includes a capacitive antenna 33 for receiving an electric, capacitive, or interrogation signal. Further, it will be 30 understood by the skilled addressee from the teaching herein that the invention is applicable to still other receiving devices, and is not limited by the choice of antenna or the specific form of interrogation signal.

WO 2004/019055 PCT/AU2003/001072 -9 The Typical Operation of Prior Art Tags Before further describing the embodiments of the invention, the operation of a typical prior art tag will be examined. A typical tag includes a circuit 5 illustrated schematically in Figure 2. Particularly, the voltage VI is induced in antenna coil by the interrogation field, and 5 the antenna coil LIis tuned by a tuning capacitor C1. Accordingly, L1 and C1 form a resonant tuned circuit, which magnifies the voltage VI by the loaded Q factor of the antenna coil. The AC voltage generated across the tuned circuit is rectified by a rectifier 6, and the DC output voltage is stored on a storage capacitor C2. The DC load of the IC is represented by RI. Figure 1I shows a circuit model for the prior art circuit 5 where corresponding features 10 are denoted by corresponding notations. The antenna coil is represented by inductance LI and the coil losses by series resistance R5. The tuning capacitance and circuit stray capacitance are represented by Cl, and the losses of the rectifier and IC circuit by R3. The resonant currents circulating in the tuned circuit formed by LI and C1 are Il; and the output current into R3 is 12. The capacitor Q factor (Qc = w.R3.Cl) normally dominates the total resonant Q factor. 15 Typically, Qc has a value of between 10 and 40. Since the ratio of Ii/12 = Q, the resonant current Il is much larger than the output current 12. In light of the above, when tags of this type are in close proximity the magnetic field generated by the resonant current couples - through mutual inductance - with proximate tags and, therefore, VI is diminished. In other words, once the tags are in close proximity - that is, 20 within about 50 mm of each other - such "interference" compromises the reliable operation of the tags. The Removal of the Resonant Capacitor It has been appreciated by the inventors that for tags operating in close proximity to each other it is important that these resonant currents are eliminated. Given this, the inventors have 25 found that it is possible to eliminate these resonant currents by disconnecting the resonant capacitor from the antenna coil. However, even with the resonant capacitor removed from prior art devices like that shown in Figure 2, the antenna current drawn by circuit 5 is still too large to allow a plurality of tags to be closely stacked. Specifically, even without a resonant capacitor, if such tags are placed within a few millimetres of each other, the tags will not operate reliably. 30 Minimizing the Current in the Second State When the antenna coil current becomes very small or, as in some cases zero, the coil becomes transparent to the interrogation field. In this state the antenna coil has (a) no effect upon the interrogation field and (b) those tags in the low current state do not interfere with the operation of those tags in the normal current state.

WO 2004/019055 PCT/AU2003/001072 -10 In the low current state, tag 1 is not fully functional. That is, the current drawn from the coil is reduced such that only necessary circuit functions are viable. In a preferred embodiment, the current is in the order of 30 iA. Ideally, the current is zero; or at least minimized as much as possible. 5 In other embodiments, the minimizing of current is realised by one or more of a variety of methodologies, including: 1. Minimising the required functions to be performed by the circuitry. 2. Utilising low power circuitry. Low power circuitry, while widely understood, are much more difficult to design than conventional circuitry. Low power circuits 10 require less current to operate and consequently draw less current. Using low power circuits for those circuits that must remain operational in the low current state reduces the current drawn during the low current state. 3. The use of onboard energy storage devices and in particular a capacitive device. On board storage devices can provide the current required to operate the circuits in 15 the low current state. For example, a capacitive device can charge up during the normal current state and use the stored charge during the low current state so as to minimise the current drawn from the antenna. Alternatively, a battery can be used to supply the low current state current. More generally, the impedance seen by the antenna coil should be as large as possible. 20 This is particularly so in the low current state. That is, the quantum of the antenna current is proportional to the quantum of the resistive and/or the reactive load as seen by the coil. When the amount of coil current is too high, coil-to-coil magnetic interference will cause the tags to stop operating reliably. Operation 25 In the Figure 3 embodiment - which does not include a resonating capacitor - voltage V1 is induced in the antenna coil Ll by the interrogation field. Further, the antenna voltage is rectified and stored on a DC storage capacitor C2. The generated current is managed by symbolic switch SW1. A. The Symbolic Switch 30 The two states can be symbolically reflected by a switch SW1 and resistors RI and R2. Importantly, these are employed to reflect the two states and are not, in fact, part of the invention.

WO 2004/019055 PCT/AU2003/001072 -11 In other words, switch SWI reflects the device's operation in the two different "states". In essence, this is further symbolically implemented by resistors RI and R2 - which are representative of the load provided by circuit 4 in the low current state and the normal current state respectively. 5 With the benefit of the teaching herein, it will be appreciated by those skilled in the art that there are many well known methods for disabling circuits and reducing their current consumption - all of which are applicable to achieve the functionality required. For example, there are various hardware and software methods for putting a microprocessor into a "standby" or a "sleep" state. 10 B. Current Input by the Symbolic Switch The change in the current drawn by circuit 4 in the low current and the normal current state corresponds to a change in the antenna coil's current. In the low current state the antenna current is tens of microamperes and in the normal current state the antenna current is hundreds of microamperes. Specifically, typical values are 70uA in the low current state and 300uA in the 15 normal current state. In Figure 3, the low current state is symbolically represented by switch SW1 being open and the current Iq being drawn through R2. In the low current state, the quiescent current Iq is symbolically drawn. The current Iq is very small and is typically a few tens of microamperes. In this embodiment, Iq symbolically represents the current used to: maintain RAM data stored in 20 CMOS memory, operate logic functions, and power analogue circuitry. Further, the normal current state is symbolically represented by SW1 being closed and reflects activation of all of circuit 4's functionality. In the normal current state, currents Ic and Iq are drawn. The total current drawn by circuit 4 in the normal current state (Iq + Ic) is typically about 300 uA, although this does vary considerably between embodiments. 25 A "Model" of Figure 3 Figure 12 illustrates a circuit model for tag 1. Particularly: (a) the voltage VI is induced in the antenna coil LI by the interrogation field. (b) Impedance Z1 represents the series impedance of the antenna coil and any other series- connected impedance. 30 (c) R4 symbolically represents the equivalent AC resistance of circuit 4. (d) Current 12 flows from the antenna coil into R4. (e) Voltage V4 across R4 symbolically represents the voltage at the antenna terminals of LI and circuit 4, which is rectified and stored on a DC storage capacitor C2 as shown in Figure 3.

WO 2004/019055 PCT/AU2003/001072 -12 Accordingly, V4 equals VI minus the volt drop in LI and ZI due to the current 12 flowing through L1 and Z1. That is: V4 = V1 - 12.(Z1 + jwL1) where jw is the complex frequency in radians per second. This equation can be rearranged 5 into the following two forms. 12= (V1 - V4)/(ZI + jwLl) and 12= Vl/(R4 + Z1 + jwLl) Adjusting 12 10 In light of the above, assuming that the voltage V1 and the inductance LI is fixed, then current 12 is adjusted by varying either V4, R4, or Z1. For instance: 1. 12 is varied by changing V4. That is, by increasing the output voltage more voltage appears at the coil terminals and less current is drawn from the antenna coil. 15 2. 12 is varied by changing R4. That is, by increasing the AC resistance of the circuit 4 less current is drawn from the antenna coil. And, 3. 12 is varied by changing Z1. That is, by inserting an extra impedance in series with ZI, a larger voltage is dropped in the antenna coil impedance and less current is drawn from the antenna coil. 20 Embodiments incorporating such techniques will be described below in the context of Figures 6, 7, and 8. It will be appreciated by the skilled addressee that elements of these embodiments may be combined to provide alternate adjustments of 12. Alternate Embodiments 25 A. Embodiments With A Voltage Multiplier In Figure 4, an integrated circuit 7 includes a voltage multiplier circuit 8 rather than a rectifier. This is advantageous, since in the absence of resonant tuning, the coil voltage is relatively low because it is not magnified by Q. To compensate, circuit 8 increases the voltage supplied to circuit 7 and allows the circuit to operate with a lower coil voltage; the lower coil 30 voltage also requiring a lower interrogation field. In Figure 5, an integrated circuit 9 includes a voltage doubler circuit 10. In other embodiments use is made of other types of voltage multipliers, such as triplers or quadruplers. Since the impedance level of the coil used in many preferred embodiments is low - in the order of 200 ohms - it is, therefore, ideally suited to a connection with a voltage multiplier.

WO 2004/019055 PCT/AU2003/001072 -13 B. Embodiments With A Transistor In Figure 6, a switch in the form of a MOSFET transistor TI, is used to select either the normal current state or the low current state. (Ti 's drive is provided by the transceiver.) When transistor TI is closed and opened, the circuit respectively acts as a voltage doubler and a full wave 5 rectifier. The voltage doubler has a voltage gain of two, and transforms the load impedance of the chip by a factor of 8. In contrast, the full wave rectifier has a voltage gain of one, and transforms the load impedance by a factor of 2. Thus, since the voltage doubler circuit draws a significantly larger current from the antenna coil, it acts as the normal current state rectifier. In contrast, the full 10 wave rectifier is switched "on" during the low current state. C. Embodiments With An Extra Impedance In Figure 6, circuit 11 includes a sub-circuit 12 that provides an extra impedance Z2 in series with the antenna coil LI when circuit 11 is in the low current state. Z2 can be a resistance, capacitance, inductance or a combination of any, or all, of these. The extra impedance causes a 15 drop in voltage across itself and reduces 12. This is advantageous for reducing the current drawn from the antenna during the low current state. In other embodiments, such as that shown in Figure 7, circuit 12 is placed on the DC side of the rectifier and a resistor R3 is used to reduce 12. D. Embodiments With a Shunt Regulator 20 The embodiment shown in Figure 8 includes a circuit 15 that utilises a shunt regulator 16 for controlling the operating voltage provided to the integrated circuit. A detailed explanation of the operation of the shunt circuit is given in US 5,045,770. In essence, the IC's operating voltage is changed such that the low current state's operating voltage, VA + VB, is higher than the normal current state's operating voltage, VB. 25 When the IC's is at the higher operating voltage, the transceiver portion of the device operates at a lower current - therefore, less current is drawn from the antenna. The low current state operating voltage is set as high as is possible given the limitations of the IC technology. In this embodiment, for example, VA + VB = 4.2 volts and VB = 2.1 volts. E. Embodiments with a Series Regulator 30 The embodiment of Figure 9 includes a circuit that utilises a series regulator for controlling the operating voltage. The input voltage to the regulator increases when the circuit toggles into the low current state.

WO 2004/019055 PCT/AU2003/001072 -14 Systems Incorporating the Device Figure 12 illustrates an application of an embodiment of the invention as an inventory system for jewels. Previously, this process has been achieved manually, and is therefore both time consuming and prone to error. 5 In this embodiment, 100 small envelopes are horizontally stacked in a cardboard box; each envelope storing a jewel and a report on the characteristics of the jewel. As is evident from Figure 13, a plurality of RFID tags I may be placed within a few millimetres of each other without impacting on the devices' reliability. Since each tag I is programmed with the contained jewel's characteristics, its uniquely 10 coded identification signal will provide the interrogator with data that is indicative not only of the identity of each tag in the box, but also of the jewel contained within each envelope. Accordingly, the whole box ofjewels is accounted for in one automatic process. There is no need to take the envelopes out of the box and separate them to "safe" distances from each other. In this way, security is more easily maintained as well. For instance, the interrogator may 15 be placed at a passage (through which the box is placed) between a safety deposit storage area and a customer service area. Preferably, the personnel progressing the box also carries a tag so that their identity may be determined. The Determination of "State" As mentioned earlier, to maximise the reliability of the operation of closely stacked or 20 spaced tags, such as those used in Figure 13, the tags operate in either of two current states. At any one time, a small proportion of the tags are in a normal current state where the tags are responsive to the interrogator, and the remainder of the tags are in a low current state where they are not fully functional. Accordingly, in the Figure 12 embodiment, where the tags must operate within a few millimetres of each other, the probability of an individual tag being in the normal state is 1/16. 25 Generally speaking, the longer the tags are disposed within the interrogation field, the lower the normal state probability may be. In other embodiments having only a few tags, the probability of the tags being in the normal state can also be decreased. In such instances, the spacing between tags can thereby be further decreased as well. The selection of state is made using a predetermined algorithm. An example of a 30 preferred algorithm is a random or a pseudo-random number algorithm. A. Autonomous Selection In a preferred embodiment, the tags randomly select their current state autonomously. That is, the tags randomly choose a current state; receive commands and/or data, and/or transmit replies; and then randomly choose a new current state.

WO 2004/019055 PCT/AU2003/001072 -15 B. Responsiveness to Interrogation Signals In alternative embodiments, the interrogation signals are used to direct tags to select a new current state, and the tags randomly choose their current state. These interrogation signals, in some embodiments, take the form of short breaks in the interrogation field. Examples of such 5 breaks include a single break and a coded break (where the codes are sequences of breaks directing the tags to perform a various current state selection). In further alternative embodiments, other forms of modulation of the interrogation field are used to direct tags in their selection of current state. Examples of such modulations include amplitude, phase, and frequency modulation. 10 C. Probabilities The precise proportion of tags selecting the normal state is not critical, except in so far that the coupling between tags is reduced sufficiently to allow reliable operation. The probabilities or proportion of operating tags should be selected to suit the number and spacing of tags and can be determined by experiment. 15 Moreover, the algorithm may be structured so that a tag will be guaranteed to have been in the normal current state at least once every "n" state selections, where "n" is the reciprocal of the probability of selecting the normal state. A simple method of ensuring this is to force the selection of the normal current state if it has not been selected after a fixed number of selections. The value of this fixed number can be selected to suit the number and spacing of tags. 20 D. Use of Unique Tag Number Alternatively, each tag selects a current state dependent upon a fixed number, such as a unique number. In such preferred embodiments, the tag uses a portion of that number to choose a current state. More particularly, in the Figure 12 embodiment, each tag's unique number 25 includes a 4-bit mask value. The 4-bit value represents the number of interrogator breaks, or commands, received before the tag enters the normal current state. The field transmitted by the interrogator can be modulated to transmit commands to the tags. Various methods of modulating the field such as pulse, amplitude, frequency and phase are widely used and understood. 30 In further embodiments, the mask may be altered each time the tag exits the normal state. In this way, adjacent tags with similar numbers are prevented from moving to the normal current state at the same time. Larger and smaller probabilities can be selected by using smaller and longer masks. The mask can also be reduced or increased in length so that probabilities of 1, %/, 4, 1/8, 1/16, and 35 1/32 can be selected by employing masks of 0, 1, 2, 3, 4 and 5 bits respectively.

WO 2004/019055 PCT/AU2003/001072 -16 Another application is illustrated in Figure 14, where tag I is shown disposed between two cut-away layers 21 and 22 of a laminated envelope 23. While tag 1 is shown in the Figure as protruding from between the layers, that is for purposes of illustration only. It will be appreciated that, in use, tag 1 is completely enclosed by the layers. Importantly, since tag 1 is operable, even 5 when in close proximity to a number of like tags, it is possible to reliably interrogate the tags. Further Applications Figure 19 depicts a system 50 according to a preferred embodiment of the invention. As shown, an interrogator 43 integrates a plurality of devices 1. For postal envelopes, the user is able to pre-program the tags 1 to include address and 10 content information to facilitate the sorting of the envelope. Moreover, in some embodiments, the tag is pre-programmed with an encrypted message for the intended recipient. For courier envelopes, the courier may pre-program the tag to include data about the intended recipient, the contents of the envelope, the priority of the required delivery, and other data. Although the tag 1 is shown sandwiched between two layers of the envelope in Figure 15, 15 in other embodiments it is attached by other means. For example, one embodiment makes use of a plastics pocket formed on the exterior layer of the envelope for selectively receiving the tag. In another embodiment, the tag is simply placed within the envelope with the other contents. Further, attached to parcels, the invention is particularly advantageous because loosely packed parcels will often lie directly adjacent to one another -without any separation. Other alternatives will also be 20 apparent to the skilled addressee in light of the teaching herein. In another embodiment of the invention, a tag is disposed within the packaging for a saleable item. Following the placement of the item into the packaging the tag is programmed to include data indicative of the quantity or quality of the contents. This allows ease of distribution and inventory control from the point of packaging to the ultimate point of sale. This embodiment 25 is particularly advantageous when applied to packaging for computer software. However, it is also applicable to other items such as compact disc's, toys, integrated circuits, books, and any other goods that are packed closely together for storage or transportation. In more complex embodiments, a number of tags are associated with a single article. In the case of an envelope for courier use, one of the tags contains data readable only by the courier 30 organisation, while another tag includes data only readable by the sender and recipient of the envelope. The Interrogator The interrogator 43 is either a fixed installation device or, in other embodiments, a handheld device. In any event, the interrogator provides an interrogation signal - preferably in the 35 form of a RF field - that is detected by, and selectively responded to, by each tag in its field.

17 Reusability and Reliability The RFID tags of the preferred embodiments provide a re-usable resource, as the tags are re-programmable. Moreover, unlike bar codes, they will not be so easily disabled through physically rough handling. 5 Other Benefits Associated with the Present System Since prior art system, tags are used to identify items such as baggage and are designed to operate at ranges of up to 1 metre, the application of such technology is thereby limited to circumstances where tags are well spaced apart. In sharp contrast, the preferred embodiments of the invention are able to be 10 stacked closely and continue to reliably operate. A typical application is the identification of RFID tags attached to bundles of letters where the tag data is used to control the automatic sorting of each letter. However, the invention is not limited to this particular field of use. For example, various aspects of the invention are applicable to systems used for identification 15 or inventory management of items such a shoe uppers, shoe soles, diamonds and jewellery. Moreover, in addition to allowing ease of inventory control, the invention facilitates the automated sorting of those articles. This is well illustrated in the context of the jewel handling system and also in the context of mail handling 20 systems - where each piece of mail includes a tag. Accordingly, the preferred embodiments may be applied advantageously to various uses such as item identification, stock control, and inventory management. By having the ability to reliably operate in "close" ranges, such as when stacked, the application's tag and system allow these processes to be done 25 in bulk and automatically - without the need for manual intervention. Accordingly, the preferred embodiments of the invention provide many significant advantages over prior art systems Although the invention has been described with reference to a number of specific examples, it will appreciated that by those skilled in the art that the 30 invention can be embodied in many other forms. "Comprises/comprising" when used in this specification is taken to specify the presence of stated features, integers, steps or components but does not

Claims

1. An identification device for receiving a first signal and transmitting a second signal, the device including: 5 a non-resonant receiving means for receiving the first signal and employing the first signal to generate a voltage; wherein the non-resonant receiving means generates a first current from the voltage; an integrated circuit; wherein the integrated circuit includes a state selection means for selecting 10 whether the device is in a first state or a second state; a connection between the non-resonant receiving means and the integrated circuit; a transmission means for generating the second signal; wherein - relative to the second state - a relatively larger amount of the first 15 current flows through the non-resonant receiving means when the device is in the first state; and wherein - relative to the first state - a relatively smaller amount of the first current flows through the non-resonant receiving means when the device is in the second state. 20

2. An identification device according to claim 1, wherein: a first probability is associated with the first state; a second probability is associated with the second state; and the first probability is lower than the second probability. 25

3. An identification device according to claim 2, wherein the first probability is at least two times lower than the second probability.

4. An identification device according to claim 2, wherein the first probability is 30 at least four times lower than the second probability.

5. An identification device according to claim 2, wherein the first probability is at least eight times lower than the second probability. 19

6. An identification device according to claim 2, wherein the first probability is at least sixteen times lower than the second probability.

7. An identification device according to any one of claims 1 to 6, wherein the 5 relatively smaller amount of current is at least less than approximately I OOpA.

8. An identification device according to any one of claims 1 to 6, wherein the relatively smaller amount of current is less than approximately 5OpA. 10

9. An identification device according to any one of claims 1 to 6, wherein the relatively smaller amount of current is less than 30 approximately pA.

10. An identification device according to any one of claims 1 to 6, wherein the relatively smaller amount of current is less than 15 approximately pA. 15

11. An identification device according to any one of claims 1 to 6, wherein the relatively smaller amount of current is less than 5 approximately pA.

12. An identification device according to any one of claims 1 to 6, wherein the 20 relatively smaller amount of current is between approximately .1pA and approximately 4.99 pA.

13. An identification device according to any one of claims I to 12, wherein the relatively smaller amount of the first current is less than 50% of the relatively 25 larger amount of the first current.

14. An identification device according to any one of claims 1 to 12, wherein the relatively smaller amount of the first current is less than 25% of the relatively larger amount of the first current. 30

15. An identification device according to any one of claims 1 to 12, wherein the relatively smaller amount of the first current is less than 5% of the relatively larger amount of the first current. 20

16. An identification device according to any one of claims 1 to 12, wherein the relatively smaller amount of the first current is less than 1% of the relatively larger amount of the first current. 5

17. An identification device according to any one of claims 2 to 16, wherein the first probability and second probability are at least partially random.

18. An identification device according to any one of claims 1 to 17, wherein: the integrated circuit has an operating cycle of a first time; 10 the device is in either the first state or the second state - and not both states-during the first time; the integrated circuit receives the first signal for a second time, and the second time is at least equal to the first time. 15

19. An identification device according to claim 18, wherein the second time is at least equal to the reciprocal of the first probability multiplied by the first time.

20. An identification device according to any one of claims I to 19, wherein the non-resonant receiving means is an antenna. 20

21. An identification device according to claim 20, wherein the antenna is a coil.

22. An identification device according to any one of claims 1 to 19, wherein the 25 non-resonant receiving means is a dipole antenna

23. An identification device according to any one of claims 1 to 19, wherein the non-resonant receiving means is a capacitive antenna 30

24. An identification device according to any one of claims 1 to 23, wherein the first signal is at least one of: an electric signal, a capacitive signal, an inductive signal, a radio signal, and a magnetic signal 21

25. An identification device according to any one of claims I to 24, wherein the connection includes a voltage multiplier.

26. An identification device according to any one of claims 1 to 24, wherein the 5 connection includes a voltage rectifier.

27. An identification device according to any one of claims I to 26, wherein the transmission means is connected to, and responsive to, a series regulator 10

28. An identification device according to any one of claims 1 to 27, wherein the device further includes a first device portion that is comprised of an impedance means in series with the non-resonant receiving means.

29. An identification device according to claim 28, wherein the impedance 15 means is at least one of: an extra resistor, a capacitor, and an inductor.

30. An identification device according to claim 28, wherein the impedance means is a switched impedance. 20

31. An identification device according to any one of claims 1 to 30, wherein the device further includes a second device portion that is comprised of the impedance means in series with the integrated circuit.

32. An identification device according to claim 31, wherein the impedance 25 means is a switched impedance.

33. An identification device according to any one of claims 1 to 32, wherein the state selection means is responsive to the first signal. 30

34. An identification device according to any one of claims I to 34, wherein the first signal includes at least one or more first signal breaks, and the state selection means is responsive to the first signal breaks. 22

35. An identification device according to any one of claims 1 to 34, wherein the device further includes a memory.

36. An identification device according to claim 35, wherein the memory 5 includes memory space for at least one of the following information units: content information, address information, and name information.

37. An identification device according to any one of claims 1 to 36, wherein the device has a thickness between .0mm and .5mm. 10

38, An identification device according to any one of claims I to 36, wherein the device has a width betweenlomm and 10cm, and a length between 60mm and 100mm. 15

39. A device according to any one of claims I to 38, wherein the integrated circuit includes an onboard power source.

40. A device according to any one of claims 1 to 39, wherein the device employs a second antenna means that is responsive to the integrated circuit, to 20 generate the second signal.

41. An identification device according to any one of claims 1 to 41, wherein the non-resonant receiving means is also the transmission means. 25

42. A device according to claim 41, wherein the transmission means is responsive to the integrated circuit for generating the second signal.

43. A device according to any one of claims 1 to 42, wherein the state selection means includes a MOSFET transistor. 30 23

44. A system for identifying articles, the system including: a signal generator for generating a first signal; a plurality of identification devices, each individual device being respectively associated with at least one article; 5 wherein each device includes: a non-resonant receiving means for receiving the first signal and employing the first signal to generate a voltage; wherein the non-resonant receiving means generates a first current from the voltage; an integrated circuit; 10 wherein the integrated circuit includes a state selection means for selecting whether the device is in a first state or a second state; a connection between the non-resonant receiving means and the integrated circuit; a transmission means for generating the second signal; 15 wherein - relative to the second state-a relatively larger amount of the first current flows through the non-resonant receiving means when the device is in the first state; and wherein - relative to the first state-a relatively smaller amount of the first current flows through the non-resonant receiving means when the device is in the 20 second state.

45. A system according to claim 44, wherein each device further includes a memory. 25

46. A system according to claim 45, wherein the memory includes memory space for at least one of the following information units: content information, address information, and name information.

47. A system according to claim 46, further including a sorting means that 30 sorts the articles according to at least one of the following information units: content information, address information, and name information. 24

48. A system according to claim 47, wherein the plurality of devices may be placed as close as 0 cm of each other without interfering with their respective non-resonant receiving means' ability to receive the first signal and their respective transmissions means' ability to generate the second signal. 5

49. A system according to claim 47, wherein the articles are documents.

50. A system according to any one of claims 44 to 47, wherein the articles are parcels. 10

51. A system according to any one of claims 44 to 47, wherein the articles are postaged articles including at least: letters, and packages.

52. A system according to any one of claims 44 to 47, wherein the articles are baggage. 15

53. A system according to any one of claims 44 to 47, wherein the articles are inventory-related items.

54. A system according to any one of claims 44 to 53, wherein: 20 a first probability is associated with the first state; a second probability is associated with the second state; and the first probability is lower than the second probability.

55. A system according to any one of claims 44 to 53, wherein the first 25 probability is at least two times lower than the second probability.

56. A system according to any one of claims 44 to 53, wherein the first probability is at least sixteen times lower than the second probability. 30

57. An identification device according to any one of claims I to 43, wherein the state selection means is comprised of a plurality of digital circuits. 25

58. An identification device according to claim 57, wherein the digital circuits are comprised of one of the following: a dedicated logic circuit consisting of logic gates, a state engine consisting of logic arrays, a micro controller, and a processor. 5

59. An identification device according to claim 57, wherein the digital circuits are comprised of a plurality of logic arrays.

60. An identification device according to claim 59, wherein the logic arrays are 10 controlled by a microcontroller.

61. An identification device according to any one of claims 1 to 43 or 57 to 60, wherein the state selection means is further arranged to select whether the device is in the first state or the second state based upon a predetermined 15 algorithm.

62. An identification device of claim 61, wherein the predetermined algorithm is based on a random or pseudo-random number. 20

63. An identification device of claim 61, wherein the predetermined algorithm is based on a unique number.

64. An identification device according to any one of claims 1 to 43 or 57 to 63, wherein the state selection means toggles between the first state and the second 25 state.

65, An identification device according to any one of claims 1 to 43 or 57 to 63, wherein the state selection means randomly selects the first state or the second state autonomously. 30

66. An identification device according to any one of claims 1 to 43 or 57 to 63, wherein the state selection means is directed to randomly selects the first state or the second state in response to an interrogation signal. 26

67. An identification device of claim 66, wherein short breaks in the interrogation signal directs the state selection means.

68. An identification device of claim 66, wherein a single break and a coded 5 break in the interrogation signal directs the state selection means.

69. An identification device according to any one of claims 1 to 43 or 57 to 66, wherein an interrogation signal is modulated. 10

70. A method of interrogating an identification device including the steps of: providing an identification device having an integrated circuit, a non resonant receiving means connected to the integrated circuit and a transmitting means; receiving a first signal within the non-resonant receiving means) and 15 employing the first signal to generate a voltage; generating a first current from the voltage; selecting a first or second state for the identification device, wherein a relatively larger amount of the first current flows through the non-resonant receiving means when the device is in the first state and wherein a relatively 20 smaller amount of the first current flows through the non-resonant receiving means when the device is in the second state such that when the identification device is in the second state it does not interfere with the operation of other identification devices in the first state. 25

71. A method as claimed in claim 70, wherein: a first probability is associated with the first state; a second probability is associated with the second state; the first probability is lower than the second probability. 30

72. A method as claimed in claim 70 or 71, wherein: the integrated circuit operates in an operating cycle having a first time; the identification device operates in either the first state or the second state and not both states during the first time; 27 the identification device receives the first signal for a second time; and the second time is at least equal to the first time.

73. A method for interrogating an identification device in close proximity to 5 other identification devices including the steps of: providing an identification device having an integrated circuit and a transmitting means; receiving a first signal within the non-resonant receiving means and employing the first signal to generate a voltage; 10 generating a first current from the voltage; randomly or pseudo-randomly selecting a first or second state for the identification device, wherein a relatively larger amount of the first current flows through the non-resonant receiving means when the device is in the first state and wherein a relatively smaller amount of the first current flows through the non 15 resonant receiving means when the device is in the second state.

74. A method as claimed in claim 73, wherein: a first probability is associated with the first state; a second probability is associated with the second state; 20 the first probability is lower than the second probability,

75. A method as claimed in claim 73 or 74, wherein: the integrated circuit operates in an operating cycle having a first time; the identification device operates in either the first state or the second state 25 and not both states during the first time; the identification device receives the first signal for a second time; and the second time is at least equal to the first time.

76. A device as claimed in any one of claims 1 to 43 or 57 to 69, wherein the 30 integrated circuit is arranged such that when the identification device is in the second state it does not interfere with the operation of other identification devices in the first state. 28

77. A system as claimed in any one of claims 44 to 56, including at least one device as claimed in any one of claims 1 to 43 or 57 to 69 or 76.

78. A device as claimed in claim 1, substantially as herein described with 5 reference to the accompanying drawings.

79. A system as claimed in claim 44 or 77, substantially as herein described with reference to the accompanying drawings. 10

80. A method as claimed in claim 70 or 73, substantially as herein described with reference to the accompanying drawings.