AU2003249656A1 - Shape based noise tolerance characterization and analysis of lsi - Google Patents

Shape based noise tolerance characterization and analysis of lsi

Info

Publication number
AU2003249656A1
AU2003249656A1 AU2003249656A AU2003249656A AU2003249656A1 AU 2003249656 A1 AU2003249656 A1 AU 2003249656A1 AU 2003249656 A AU2003249656 A AU 2003249656A AU 2003249656 A AU2003249656 A AU 2003249656A AU 2003249656 A1 AU2003249656 A1 AU 2003249656A1
Authority
AU
Australia
Prior art keywords
lsi
analysis
shape based
noise tolerance
based noise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003249656A
Other versions
AU2003249656A8 (en
Inventor
I-Hsien Chen
Jianlin Wei
Lifeng Wu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cadence Design Systems Inc
Original Assignee
Cadence Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/340,221 external-priority patent/US6826736B2/en
Application filed by Cadence Design Systems Inc filed Critical Cadence Design Systems Inc
Publication of AU2003249656A1 publication Critical patent/AU2003249656A1/en
Publication of AU2003249656A8 publication Critical patent/AU2003249656A8/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
AU2003249656A 2002-06-07 2003-05-28 Shape based noise tolerance characterization and analysis of lsi Abandoned AU2003249656A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US38729402P 2002-06-07 2002-06-07
US60/387,294 2002-06-07
US10/340,221 US6826736B2 (en) 2002-06-07 2003-01-10 Shape based noise tolerance characterization and analysis of LSI
US10/340,221 2003-01-10
PCT/US2003/016793 WO2003105188A2 (en) 2002-06-07 2003-05-28 Shape based noise tolerance characterization and analysis of lsi

Publications (2)

Publication Number Publication Date
AU2003249656A1 true AU2003249656A1 (en) 2003-12-22
AU2003249656A8 AU2003249656A8 (en) 2003-12-22

Family

ID=29739366

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003249656A Abandoned AU2003249656A1 (en) 2002-06-07 2003-05-28 Shape based noise tolerance characterization and analysis of lsi

Country Status (3)

Country Link
AU (1) AU2003249656A1 (en)
TW (1) TW200406707A (en)
WO (1) WO2003105188A2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6493853B1 (en) * 1999-07-15 2002-12-10 Texas Instruments Incorporated Cell-based noise characterization and evaluation

Also Published As

Publication number Publication date
WO2003105188A2 (en) 2003-12-18
AU2003249656A8 (en) 2003-12-22
TW200406707A (en) 2004-05-01
WO2003105188A3 (en) 2005-01-27

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase