AU2003246832A1 - Method for coding and/or decoding error correcting codes, and corresponding devices and signal - Google Patents

Method for coding and/or decoding error correcting codes, and corresponding devices and signal

Info

Publication number
AU2003246832A1
AU2003246832A1 AU2003246832A AU2003246832A AU2003246832A1 AU 2003246832 A1 AU2003246832 A1 AU 2003246832A1 AU 2003246832 A AU2003246832 A AU 2003246832A AU 2003246832 A AU2003246832 A AU 2003246832A AU 2003246832 A1 AU2003246832 A1 AU 2003246832A1
Authority
AU
Australia
Prior art keywords
coding
signal
error correcting
decoding error
corresponding devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003246832A
Inventor
Emmanuel Boutillon
Vincent Gaudet
David Gnaedig
Glenn Gulak
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Universite de Bretagne Sud
Original Assignee
Universite de Bretagne Sud
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Universite de Bretagne Sud filed Critical Universite de Bretagne Sud
Publication of AU2003246832A1 publication Critical patent/AU2003246832A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2771—Internal interleaver for turbo codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6566—Implementations concerning memory access contentions
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B2020/10935—Digital recording or reproducing wherein a time constraint must be met
    • G11B2020/10944—Real-time recording or reproducing, e.g. for ensuring seamless playback of AV data

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
AU2003246832A 2002-04-16 2003-04-14 Method for coding and/or decoding error correcting codes, and corresponding devices and signal Abandoned AU2003246832A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0204764A FR2838581B1 (en) 2002-04-16 2002-04-16 METHOD FOR ENCODING AND / OR DECODING CORRECTIVE ERROR CODES, DEVICES AND SIGNAL THEREOF
FR02/04764 2002-04-16
PCT/FR2003/001188 WO2003088504A1 (en) 2002-04-16 2003-04-14 Method for coding and/or decoding error correcting codes, and corresponding devices and signal

Publications (1)

Publication Number Publication Date
AU2003246832A1 true AU2003246832A1 (en) 2003-10-27

Family

ID=28459899

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003246832A Abandoned AU2003246832A1 (en) 2002-04-16 2003-04-14 Method for coding and/or decoding error correcting codes, and corresponding devices and signal

Country Status (3)

Country Link
AU (1) AU2003246832A1 (en)
FR (1) FR2838581B1 (en)
WO (1) WO2003088504A1 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7577207B2 (en) 2002-07-03 2009-08-18 Dtvg Licensing, Inc. Bit labeling for amplitude phase shift constellation used with low density parity check (LDPC) codes
ATE360284T1 (en) 2002-07-03 2007-05-15 Directv Group Inc CODING OF LDPC (LOW-DENSITY PARITY CHECK) CODES BY USING A STRUCTURED PARITY CHECK MATRIX
US7020829B2 (en) 2002-07-03 2006-03-28 Hughes Electronics Corporation Method and system for decoding low density parity check (LDPC) codes
US7864869B2 (en) 2002-07-26 2011-01-04 Dtvg Licensing, Inc. Satellite communication system utilizing low density parity check codes
US20040019845A1 (en) 2002-07-26 2004-01-29 Hughes Electronics Method and system for generating low density parity check codes
WO2006082923A1 (en) * 2005-02-03 2006-08-10 Matsushita Electric Industrial Co., Ltd. Parallel interleaver, parallel deinterleaver, and interleave method
FR2883121B1 (en) * 2005-03-11 2007-04-27 France Telecom METHOD AND DEVICE FOR DECODING WHEEL CODES
FR2915641B1 (en) 2007-04-30 2009-08-07 St Microelectronics Sa METHOD AND DEVICE FOR INTERLEAVING DATA
FR2987527B1 (en) 2012-02-23 2014-02-21 Univ Bretagne Sud SELF-CONFIGURABLE DEVICE FOR INTERLACING / UNLOCATION OF DATA FRAMES

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4547882A (en) * 1983-03-01 1985-10-15 The Board Of Trustees Of The Leland Stanford Jr. University Error detecting and correcting memories
US4882733A (en) * 1987-03-13 1989-11-21 Ford Aerospace Corporation Method and apparatus for combining encoding and modulation
US5157671A (en) * 1990-05-29 1992-10-20 Space Systems/Loral, Inc. Semi-systolic architecture for decoding error-correcting codes
FR2675971B1 (en) * 1991-04-23 1993-08-06 France Telecom CORRECTIVE ERROR CODING METHOD WITH AT LEAST TWO SYSTEMIC CONVOLUTIVE CODES IN PARALLEL, ITERATIVE DECODING METHOD, CORRESPONDING DECODING MODULE AND DECODER.

Also Published As

Publication number Publication date
FR2838581A1 (en) 2003-10-17
WO2003088504A1 (en) 2003-10-23
FR2838581B1 (en) 2005-07-08

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase