AU2003246719A1 - A method of increasing the area of a useful layer of material transferred onto a support - Google Patents

A method of increasing the area of a useful layer of material transferred onto a support

Info

Publication number
AU2003246719A1
AU2003246719A1 AU2003246719A AU2003246719A AU2003246719A1 AU 2003246719 A1 AU2003246719 A1 AU 2003246719A1 AU 2003246719 A AU2003246719 A AU 2003246719A AU 2003246719 A AU2003246719 A AU 2003246719A AU 2003246719 A1 AU2003246719 A1 AU 2003246719A1
Authority
AU
Australia
Prior art keywords
outline
substrate
flat
zone
increasing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003246719A
Inventor
Christophe Maleville
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR0209020A external-priority patent/FR2842649B1/en
Application filed by Soitec SA filed Critical Soitec SA
Publication of AU2003246719A1 publication Critical patent/AU2003246719A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Laminated Bodies (AREA)
  • Coating Apparatus (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Manipulator (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

The invention relates to a method of increasing the area of a useful layer (63) of material coming from a source substrate (6) and which has been transferred onto a support substrate (7). The invention is remarkable in that one of the two substrates is surrounded by a primary chamfer (74, 64), its front face presenting at least a flat central zone (70) of outline (C7), in that the front face of the other substrate is a flat zone (67) bordered by a peripheral side face (66), perpendicular or quasi-perpendicular thereto, the outer outline (C"6) of said flat zone (67) presenting dimensions greater than the dimensions of the outer outline (C7) of said flat central zone (70) of the first substrate (7), and in that during bonding, the two substrates (6, 7) are applied one against the other in such a manner that the outline (C7) of said flat central zone (70) is inscribed within the outline (C"6) of said flat zone (67). The invention is applicable to fabricating a composite substrate for electronics, optics, or optoelectronics.
AU2003246719A 2002-07-17 2003-07-16 A method of increasing the area of a useful layer of material transferred onto a support Abandoned AU2003246719A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
FR0209020A FR2842649B1 (en) 2002-07-17 2002-07-17 METHOD OF INCREASING THE AREA OF A USEFUL LAYER OF MATERIAL REFLECTED ON A SUPPORT
FR0209020 2002-07-17
US47313703P 2003-05-27 2003-05-27
US60/473,137 2003-05-27
PCT/EP2003/007856 WO2004025722A1 (en) 2002-07-17 2003-07-16 A method of increasing the area of a useful layer of material transferred onto a support

Publications (1)

Publication Number Publication Date
AU2003246719A1 true AU2003246719A1 (en) 2004-04-30

Family

ID=31995626

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003246719A Abandoned AU2003246719A1 (en) 2002-07-17 2003-07-16 A method of increasing the area of a useful layer of material transferred onto a support

Country Status (7)

Country Link
EP (1) EP1522098B1 (en)
JP (1) JP4652053B2 (en)
AT (1) ATE465513T1 (en)
AU (1) AU2003246719A1 (en)
DE (1) DE60332241D1 (en)
TW (1) TWI266381B (en)
WO (1) WO2004025722A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004008527A1 (en) * 2002-07-17 2004-01-22 S.O.I.Tec Silicon On Insulator Technologies A method of increasing the area of a useful layer of material transferred onto a support
WO2010050629A1 (en) * 2008-10-27 2010-05-06 Man Soo Choi Method of treating fabric conditioner for washable silk products
CN106847739B (en) * 2015-12-04 2018-08-31 上海新微技术研发中心有限公司 Method for manufacturing silicon-on-insulator material
TWI668739B (en) * 2018-04-03 2019-08-11 環球晶圓股份有限公司 Epitaxy substrate and method of manufacturing the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0636413B2 (en) * 1990-03-29 1994-05-11 信越半導体株式会社 Manufacturing method of semiconductor element forming substrate
JP2825048B2 (en) * 1992-08-10 1998-11-18 信越半導体株式会社 Semiconductor silicon substrate
US6664169B1 (en) * 1999-06-08 2003-12-16 Canon Kabushiki Kaisha Process for producing semiconductor member, process for producing solar cell, and anodizing apparatus
JP3542521B2 (en) * 1999-06-08 2004-07-14 キヤノン株式会社 Method for producing semiconductor substrate and solar cell and anodizing apparatus
WO2001073831A1 (en) * 2000-03-29 2001-10-04 Shin-Etsu Handotai Co., Ltd. Production method for silicon wafer and soi wafer, and soi wafer
JP4846915B2 (en) * 2000-03-29 2011-12-28 信越半導体株式会社 Manufacturing method of bonded wafer
JP2001284622A (en) * 2000-03-31 2001-10-12 Canon Inc Semiconductor member manufacturing method and solar cell manufacturing method

Also Published As

Publication number Publication date
EP1522098B1 (en) 2010-04-21
JP4652053B2 (en) 2011-03-16
DE60332241D1 (en) 2010-06-02
JP2005533394A (en) 2005-11-04
TW200423294A (en) 2004-11-01
TWI266381B (en) 2006-11-11
EP1522098A1 (en) 2005-04-13
WO2004025722A1 (en) 2004-03-25
ATE465513T1 (en) 2010-05-15

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase