AU2002361011A1 - Arithmetic-logic unit and method for combining a first operand with a second operand - Google Patents

Arithmetic-logic unit and method for combining a first operand with a second operand

Info

Publication number
AU2002361011A1
AU2002361011A1 AU2002361011A AU2002361011A AU2002361011A1 AU 2002361011 A1 AU2002361011 A1 AU 2002361011A1 AU 2002361011 A AU2002361011 A AU 2002361011A AU 2002361011 A AU2002361011 A AU 2002361011A AU 2002361011 A1 AU2002361011 A1 AU 2002361011A1
Authority
AU
Australia
Prior art keywords
operand
arithmetic
combining
logic unit
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002361011A
Inventor
Berndt Gammel
Franz Klug
Oliver Kniffler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of AU2002361011A1 publication Critical patent/AU2002361011A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Storage Device Security (AREA)
  • Complex Calculations (AREA)
AU2002361011A 2002-01-16 2002-12-18 Arithmetic-logic unit and method for combining a first operand with a second operand Abandoned AU2002361011A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10201444A DE10201444A1 (en) 2002-01-16 2002-01-16 Calculator and method for combining a first operand with a second operand
DE10201444.2 2002-01-16
PCT/EP2002/014492 WO2003060694A1 (en) 2002-01-16 2002-12-18 Arithmetic-logic unit and method for combining a first operand with a second operand

Publications (1)

Publication Number Publication Date
AU2002361011A1 true AU2002361011A1 (en) 2003-07-30

Family

ID=7712271

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002361011A Abandoned AU2002361011A1 (en) 2002-01-16 2002-12-18 Arithmetic-logic unit and method for combining a first operand with a second operand

Country Status (4)

Country Link
EP (1) EP1466245B1 (en)
AU (1) AU2002361011A1 (en)
DE (2) DE10201444A1 (en)
WO (1) WO2003060694A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006006057B4 (en) * 2006-02-09 2007-12-27 Infineon Technologies Ag Data encryption apparatus and method for encrypting data
US7921148B2 (en) * 2006-08-09 2011-04-05 Infineon Technologies Ag Standard cell for arithmetic logic unit and chip card controller

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3123977B2 (en) * 1998-06-04 2001-01-15 日本電気株式会社 Programmable function block

Also Published As

Publication number Publication date
WO2003060694A1 (en) 2003-07-24
DE10201444A1 (en) 2003-07-31
EP1466245A1 (en) 2004-10-13
EP1466245B1 (en) 2005-04-27
DE50202957D1 (en) 2005-06-02

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase