AU2002317928A1 - Cryptographic processing accelerator board - Google Patents

Cryptographic processing accelerator board

Info

Publication number
AU2002317928A1
AU2002317928A1 AU2002317928A AU2002317928A AU2002317928A1 AU 2002317928 A1 AU2002317928 A1 AU 2002317928A1 AU 2002317928 A AU2002317928 A AU 2002317928A AU 2002317928 A AU2002317928 A AU 2002317928A AU 2002317928 A1 AU2002317928 A1 AU 2002317928A1
Authority
AU
Australia
Prior art keywords
cryptographic processing
processing accelerator
accelerator board
board
cryptographic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002317928A
Other languages
English (en)
Other versions
AU2002317928A8 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ZENCOD SA
Original Assignee
Zencod S A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zencod S A filed Critical Zencod S A
Publication of AU2002317928A8 publication Critical patent/AU2002317928A8/xx
Publication of AU2002317928A1 publication Critical patent/AU2002317928A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5052—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination using carry completion detection, either over all stages or at sample stages only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
AU2002317928A 2001-06-13 2002-06-13 Cryptographic processing accelerator board Abandoned AU2002317928A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US29781801P 2001-06-13 2001-06-13
US60/297,818 2001-06-13
US17124302A 2002-06-13 2002-06-13
US10/171,243 2002-06-13
PCT/FR2002/002036 WO2003040911A2 (fr) 2001-06-13 2002-06-13 Carte d'acceleration de traitement cryptographique

Publications (2)

Publication Number Publication Date
AU2002317928A8 AU2002317928A8 (en) 2003-05-19
AU2002317928A1 true AU2002317928A1 (en) 2003-05-19

Family

ID=26866880

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002317928A Abandoned AU2002317928A1 (en) 2001-06-13 2002-06-13 Cryptographic processing accelerator board

Country Status (3)

Country Link
EP (1) EP1417566A2 (fr)
AU (1) AU2002317928A1 (fr)
WO (1) WO2003040911A2 (fr)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1038941B (it) * 1974-07-06 1979-11-30 Ibm Sistema di calcolo perfezionato
EP0098692A3 (fr) * 1982-07-01 1986-04-16 Hewlett-Packard Company Dispositif d'addition d'un premier et d'un second opérandes binaires
GB9707861D0 (en) * 1997-04-18 1997-06-04 Certicom Corp Arithmetic processor
US6088800A (en) * 1998-02-27 2000-07-11 Mosaid Technologies, Incorporated Encryption processor with shared memory interconnect

Also Published As

Publication number Publication date
WO2003040911A2 (fr) 2003-05-15
AU2002317928A8 (en) 2003-05-19
WO2003040911A3 (fr) 2004-02-26
EP1417566A2 (fr) 2004-05-12

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase