AU2002241528A1 - Cache retry request queue - Google Patents

Cache retry request queue

Info

Publication number
AU2002241528A1
AU2002241528A1 AU2002241528A AU4152802A AU2002241528A1 AU 2002241528 A1 AU2002241528 A1 AU 2002241528A1 AU 2002241528 A AU2002241528 A AU 2002241528A AU 4152802 A AU4152802 A AU 4152802A AU 2002241528 A1 AU2002241528 A1 AU 2002241528A1
Authority
AU
Australia
Prior art keywords
cache
request queue
retry request
retry
queue
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002241528A
Inventor
John G. Favor
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Redback Networks Inc
Original Assignee
Redback Networks Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Redback Networks Inc filed Critical Redback Networks Inc
Publication of AU2002241528A1 publication Critical patent/AU2002241528A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0857—Overlapped cache accessing, e.g. pipeline by multiple requestors

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU2002241528A 2000-12-18 2001-11-27 Cache retry request queue Abandoned AU2002241528A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/740,658 2000-12-18
US09/740,658 US6732236B2 (en) 2000-12-18 2000-12-18 Cache retry request queue
PCT/US2001/044608 WO2002050689A1 (en) 2000-12-18 2001-11-27 Cache retry request queue

Publications (1)

Publication Number Publication Date
AU2002241528A1 true AU2002241528A1 (en) 2002-07-01

Family

ID=24977489

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002241528A Abandoned AU2002241528A1 (en) 2000-12-18 2001-11-27 Cache retry request queue

Country Status (3)

Country Link
US (1) US6732236B2 (en)
AU (1) AU2002241528A1 (en)
WO (1) WO2002050689A1 (en)

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6768358B2 (en) * 2001-08-29 2004-07-27 Analog Devices, Inc. Phase locked loop fast power up methods and apparatus
JP4417715B2 (en) * 2001-09-14 2010-02-17 サン・マイクロシステムズ・インコーポレーテッド Method and apparatus for decoupling tag and data access in cache memory
US7203817B2 (en) * 2001-09-24 2007-04-10 Broadcom Corporation Power consumption reduction in a pipeline by stalling instruction issue on a load miss
US20040153611A1 (en) * 2003-02-04 2004-08-05 Sujat Jamil Methods and apparatus for detecting an address conflict
US20050138290A1 (en) * 2003-12-23 2005-06-23 Intel Corporation System and method for instruction rescheduling
US20050193172A1 (en) * 2004-02-26 2005-09-01 Anoop Mukker Method and apparatus for splitting a cache operation into multiple phases and multiple clock domains
US7363468B2 (en) 2004-11-18 2008-04-22 International Business Machines Corporation Load address dependency mechanism system and method in a high frequency, low power processor system
US7406571B2 (en) * 2006-02-09 2008-07-29 International Business Machines Corporation Memory system and method for controlling the same, and method for maintaining data coherency
US20090006777A1 (en) * 2007-06-28 2009-01-01 Donley Greggory D Apparatus for reducing cache latency while preserving cache bandwidth in a cache subsystem of a processor
US20090006756A1 (en) * 2007-06-29 2009-01-01 Donley Greggory D Cache memory having configurable associativity
US8006042B2 (en) * 2007-11-26 2011-08-23 Globalfoundries Inc. Floating point bypass retry
US20090157982A1 (en) * 2007-12-18 2009-06-18 Macinnis Alexander G Multiple miss cache
JP2010033480A (en) * 2008-07-31 2010-02-12 Sony Corp Cache memory and cache memory control apparatus
US20100169578A1 (en) * 2008-12-31 2010-07-01 Texas Instruments Incorporated Cache tag memory
US9311251B2 (en) 2012-08-27 2016-04-12 Apple Inc. System cache with sticky allocation
US9158685B2 (en) * 2012-09-11 2015-10-13 Apple Inc. System cache with cache hint control
US20140089600A1 (en) * 2012-09-27 2014-03-27 Apple Inc. System cache with data pending state
US9201796B2 (en) * 2012-09-27 2015-12-01 Apple Inc. System cache with speculative read engine
US9223780B2 (en) * 2012-12-19 2015-12-29 Microsoft Technology Licensing, Llc Non-blocking caching technique
US9785545B2 (en) * 2013-07-15 2017-10-10 Cnex Labs, Inc. Method and apparatus for providing dual memory access to non-volatile memory
US9710226B1 (en) * 2013-07-16 2017-07-18 Rambus Inc. Unsuccessful write retry buffer
US10360159B1 (en) * 2013-12-12 2019-07-23 Groupon, Inc. System, method, apparatus, and computer program product for providing a cache mechanism
US9665372B2 (en) 2014-05-12 2017-05-30 International Business Machines Corporation Parallel slice processor with dynamic instruction stream mapping
US9672043B2 (en) 2014-05-12 2017-06-06 International Business Machines Corporation Processing of multiple instruction streams in a parallel slice processor
KR102106261B1 (en) 2014-06-17 2020-05-04 삼성전자주식회사 Method of operating memory controller and methods for devices having same
US9760375B2 (en) 2014-09-09 2017-09-12 International Business Machines Corporation Register files for storing data operated on by instructions of multiple widths
US9720696B2 (en) 2014-09-30 2017-08-01 International Business Machines Corporation Independent mapping of threads
US9977678B2 (en) 2015-01-12 2018-05-22 International Business Machines Corporation Reconfigurable parallel execution and load-store slice processor
US10133576B2 (en) 2015-01-13 2018-11-20 International Business Machines Corporation Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries
US10133581B2 (en) 2015-01-13 2018-11-20 International Business Machines Corporation Linkable issue queue parallel execution slice for a processor
US9983875B2 (en) 2016-03-04 2018-05-29 International Business Machines Corporation Operation of a multi-slice processor preventing early dependent instruction wakeup
US10037211B2 (en) 2016-03-22 2018-07-31 International Business Machines Corporation Operation of a multi-slice processor with an expanded merge fetching queue
US10346174B2 (en) 2016-03-24 2019-07-09 International Business Machines Corporation Operation of a multi-slice processor with dynamic canceling of partial loads
US10761854B2 (en) 2016-04-19 2020-09-01 International Business Machines Corporation Preventing hazard flushes in an instruction sequencing unit of a multi-slice processor
US10037229B2 (en) 2016-05-11 2018-07-31 International Business Machines Corporation Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions
US9934033B2 (en) 2016-06-13 2018-04-03 International Business Machines Corporation Operation of a multi-slice processor implementing simultaneous two-target loads and stores
US10042647B2 (en) 2016-06-27 2018-08-07 International Business Machines Corporation Managing a divided load reorder queue
US10318419B2 (en) 2016-08-08 2019-06-11 International Business Machines Corporation Flush avoidance in a load store unit
US10146440B2 (en) * 2016-12-20 2018-12-04 Intel Corporation Apparatus, system and method for offloading collision check operations in a storage device
US10474575B2 (en) * 2017-04-10 2019-11-12 Arm Limited Cache-based communication between execution threads of a data processing system
US11106609B2 (en) * 2019-02-28 2021-08-31 Micron Technology, Inc. Priority scheduling in queues to access cache data in a memory sub-system
US11288199B2 (en) 2019-02-28 2022-03-29 Micron Technology, Inc. Separate read-only cache and write-read cache in a memory sub-system
US10970222B2 (en) 2019-02-28 2021-04-06 Micron Technology, Inc. Eviction of a cache line based on a modification of a sector of the cache line
US11403103B2 (en) 2020-04-14 2022-08-02 Shanghai Zhaoxin Semiconductor Co., Ltd. Microprocessor with multi-step ahead branch predictor and having a fetch-target queue between the branch predictor and instruction cache
US12099845B2 (en) * 2022-06-16 2024-09-24 International Business Machines Corporation Load reissuing using an alternate issue queue
CN116107929B (en) * 2023-04-13 2023-07-25 摩尔线程智能科技(北京)有限责任公司 Data access method and device, storage medium and electronic equipment

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5432918A (en) * 1990-06-29 1995-07-11 Digital Equipment Corporation Method and apparatus for ordering read and write operations using conflict bits in a write queue
EP0463966B1 (en) * 1990-06-29 1998-11-25 Digital Equipment Corporation High-performance multi-processor having floating point unit and operation method
US5404483A (en) * 1990-06-29 1995-04-04 Digital Equipment Corporation Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills
CA2045756C (en) * 1990-06-29 1996-08-20 Gregg Bouchard Combined queue for invalidates and return data in multiprocessor system
DE69127936T2 (en) * 1990-06-29 1998-05-07 Digital Equipment Corp Bus protocol for processor with write-back cache
TW243509B (en) 1994-01-31 1995-03-21 Ibm Data processor with memory cache and method of operation
US6145054A (en) 1998-01-21 2000-11-07 Sun Microsystems, Inc. Apparatus and method for handling multiple mergeable misses in a non-blocking cache
US6148372A (en) 1998-01-21 2000-11-14 Sun Microsystems, Inc. Apparatus and method for detection and recovery from structural stalls in a multi-level non-blocking cache system
US6339813B1 (en) * 2000-01-07 2002-01-15 International Business Machines Corporation Memory system for permitting simultaneous processor access to a cache line and sub-cache line sectors fill and writeback to a system memory

Also Published As

Publication number Publication date
WO2002050689A1 (en) 2002-06-27
WO2002050689A9 (en) 2003-01-03
US20020078302A1 (en) 2002-06-20
US6732236B2 (en) 2004-05-04

Similar Documents

Publication Publication Date Title
AU2002241528A1 (en) Cache retry request queue
AU6383001A (en) Cache time determination
AU2002212464A1 (en) Computer system
AU2002353358A1 (en) Cache on demand
AU1442201A (en) Hypervideo: information retrieval at user request
AU2002332604A1 (en) Content ownership resolution
GB0106608D0 (en) Computer system
AU2001245806A1 (en) Transactional file system
AU2001229574A1 (en) Split embedded dram processor
AU2001294073A1 (en) Processor architecture
AU2001295768A1 (en) Processor architecture
AU2001236480A1 (en) Host-specified usb device requests
AU1880901A (en) Hand held data processor unit
AU2001291033A1 (en) Web-based transactional system
AU2001264671A1 (en) Latency monitor
AU7431901A (en) Coherence-free cache
AU2001293840A1 (en) Reduced-noise device
AU2002241767A1 (en) Concurrent-multitasking processor
AU2001247447A1 (en) Mocvd-grown emode higfet buffer
AU2001276768A1 (en) Touch pad system
AU2001260461A1 (en) Location system
AU4322300A (en) Divided buffer
AU2001296039A1 (en) Computer
AU2001279941A1 (en) Support device
GB0009941D0 (en) Computer system