AU2002232741A1 - Interconnect model compiler - Google Patents

Interconnect model compiler

Info

Publication number
AU2002232741A1
AU2002232741A1 AU2002232741A AU3274102A AU2002232741A1 AU 2002232741 A1 AU2002232741 A1 AU 2002232741A1 AU 2002232741 A AU2002232741 A AU 2002232741A AU 3274102 A AU3274102 A AU 3274102A AU 2002232741 A1 AU2002232741 A1 AU 2002232741A1
Authority
AU
Australia
Prior art keywords
interconnect model
model compiler
compiler
interconnect
model
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002232741A
Inventor
John F. Croix
Robert Jones
Curtis L. Ratzlaf
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Silicon Metrics Corp
Original Assignee
Silicon Metrics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Metrics Corp filed Critical Silicon Metrics Corp
Publication of AU2002232741A1 publication Critical patent/AU2002232741A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
AU2002232741A 2000-11-07 2001-11-07 Interconnect model compiler Abandoned AU2002232741A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/707,757 2000-11-07
US09/707,757 US6766506B1 (en) 2000-11-07 2000-11-07 Interconnect model compiler
PCT/US2001/049862 WO2002039267A2 (en) 2000-11-07 2001-11-07 Interconnect model compiler

Publications (1)

Publication Number Publication Date
AU2002232741A1 true AU2002232741A1 (en) 2002-05-21

Family

ID=24843050

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002232741A Abandoned AU2002232741A1 (en) 2000-11-07 2001-11-07 Interconnect model compiler

Country Status (3)

Country Link
US (1) US6766506B1 (en)
AU (1) AU2002232741A1 (en)
WO (1) WO2002039267A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7363609B2 (en) * 2001-07-26 2008-04-22 International Business Machines Corporation Method of logic circuit synthesis and design using a dynamic circuit library
US7051318B1 (en) * 2001-10-09 2006-05-23 Lsi Logic Corporation Web based OLA memory generator
US7155691B2 (en) * 2003-06-06 2006-12-26 Nascentric, Inc. Apparatus and methods for compiled static timing analysis
US7131079B2 (en) * 2004-05-04 2006-10-31 Faraday Technology Corp. Method of generating protected standard delay format file
US8453136B1 (en) * 2007-03-06 2013-05-28 Cadence Design Systems, Inc. Change tracking and incremental synchronization of EDA design and technology data
US7746473B2 (en) * 2007-05-24 2010-06-29 Applied Materials, Inc. Full spectrum adaptive filtering (FSAF) for low open area endpoint detection
US20090158265A1 (en) * 2007-12-13 2009-06-18 Matthew Fenton Davis Implementation of advanced endpoint functions within third party software by using a plug-in approach
US11443089B1 (en) * 2021-03-15 2022-09-13 Amazon Technologies, Inc. Timing verification of non-standard library blocks

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5410490A (en) * 1991-09-03 1995-04-25 Hewlett-Packard Company Electromigration verification method and apparatus
US5828580A (en) * 1994-11-08 1998-10-27 Epic Design Technology, Inc. Connectivity-based approach for extracting parasitic layout in an integrated circuit
US5920484A (en) 1996-12-02 1999-07-06 Motorola Inc. Method for generating a reduced order model of an electronic circuit
JPH10301979A (en) * 1997-04-30 1998-11-13 Oki Electric Ind Co Ltd Method and device for extracting model parameter
JP3634556B2 (en) * 1997-05-12 2005-03-30 キヤノン株式会社 Image processing method and system
US5878053A (en) 1997-06-09 1999-03-02 Synopsys, Inc. Hierarchial power network simulation and analysis tool for reliability testing of deep submicron IC designs
US6072945A (en) 1997-06-26 2000-06-06 Sun Microsystems Inc. System for automated electromigration verification
US6279142B1 (en) * 1998-10-02 2001-08-21 International Business Machines Corporation Method of on-chip interconnect design
US6314546B1 (en) * 1999-03-08 2001-11-06 Silicon Graphics, Inc. Interconnect capacitive effects estimation
US6499131B1 (en) * 1999-07-15 2002-12-24 Texas Instruments Incorporated Method for verification of crosstalk noise in a CMOS design

Also Published As

Publication number Publication date
WO2002039267A3 (en) 2003-04-24
US6766506B1 (en) 2004-07-20
WO2002039267A2 (en) 2002-05-16
WO2002039267A9 (en) 2002-07-25

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