AU2002229007A1 - Multiple device scan chain emulation/debugging - Google Patents

Multiple device scan chain emulation/debugging

Info

Publication number
AU2002229007A1
AU2002229007A1 AU2002229007A AU2900702A AU2002229007A1 AU 2002229007 A1 AU2002229007 A1 AU 2002229007A1 AU 2002229007 A AU2002229007 A AU 2002229007A AU 2900702 A AU2900702 A AU 2900702A AU 2002229007 A1 AU2002229007 A1 AU 2002229007A1
Authority
AU
Australia
Prior art keywords
debugging
scan chain
multiple device
device scan
emulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002229007A
Inventor
James J. O'brien
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wind River Systems Inc
Original Assignee
Wind River Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wind River Systems Inc filed Critical Wind River Systems Inc
Publication of AU2002229007A1 publication Critical patent/AU2002229007A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
    • G01R31/2815—Functional tests, e.g. boundary scans, using the normal I/O contacts
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
AU2002229007A 2000-11-21 2001-11-16 Multiple device scan chain emulation/debugging Abandoned AU2002229007A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US25231600P 2000-11-21 2000-11-21
US60252316 2000-11-21
US09/921,250 US6886110B2 (en) 2000-11-21 2001-08-02 Multiple device scan chain emulation/debugging
US09921250 2001-08-02
PCT/US2001/048003 WO2002042949A1 (en) 2000-11-21 2001-11-16 Multiple device scan chain emulation/debugging

Publications (1)

Publication Number Publication Date
AU2002229007A1 true AU2002229007A1 (en) 2002-06-03

Family

ID=26942230

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002229007A Abandoned AU2002229007A1 (en) 2000-11-21 2001-11-16 Multiple device scan chain emulation/debugging

Country Status (3)

Country Link
US (2) US6886110B2 (en)
AU (1) AU2002229007A1 (en)
WO (1) WO2002042949A1 (en)

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US6886110B2 (en) * 2000-11-21 2005-04-26 Wind River Systems, Inc. Multiple device scan chain emulation/debugging
US20030225566A1 (en) * 2002-06-03 2003-12-04 O'brein James J. JTAG server
US7246282B2 (en) * 2003-06-25 2007-07-17 Hewlett-Packard Development Company, L.P. Bypassing a device in a scan chain
US7269771B1 (en) * 2003-09-30 2007-09-11 Lattice Semiconductor Corporation Semiconductor device adapted for forming multiple scan chains
US7752004B1 (en) * 2004-01-09 2010-07-06 Cisco Technology, Inc. Method and apparatus for configuring plurality of devices on printed circuit board into desired test port configuration
JP2007524088A (en) * 2004-01-19 2007-08-23 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Inspection architecture and method
US20070136631A1 (en) * 2005-11-19 2007-06-14 Govani Atul V Method and system for testing backplanes utilizing a boundary scan protocol
US9104894B2 (en) * 2005-12-16 2015-08-11 Hewlett-Packard Development Company, L.P. Hardware enablement using an interface
US7448635B2 (en) * 2006-02-02 2008-11-11 Yamaha Hatsudoki Kabushiki Kaisha Recreational vehicle
US7650546B2 (en) * 2006-03-17 2010-01-19 Alcatel Lucent Flexible JTAG architecture
US7676371B2 (en) * 2006-06-13 2010-03-09 Nuance Communications, Inc. Oral modification of an ASR lexicon of an ASR engine
US7657854B2 (en) * 2006-11-24 2010-02-02 Freescale Semiconductor, Inc. Method and system for designing test circuit in a system on chip
US7610534B1 (en) * 2007-03-20 2009-10-27 Xilinx, Inc. Determining a length of the instruction register of an unidentified device on a scan chain
US8261143B2 (en) * 2007-05-07 2012-09-04 Texas Instruments Incorporated Select signal and component override signal controlling multiplexing TDI/TDO
US20100031077A1 (en) * 2008-07-29 2010-02-04 Swoboda Gary L Alternate Signaling Mechanism Using Clock and Data
US20100175012A1 (en) * 2009-01-06 2010-07-08 Allstrom Peter E System and Method for Remote Monitoring and Control of Field Device
US8447554B2 (en) * 2009-09-28 2013-05-21 Mohammed Reza Emami System, method and computer program for remotely testing system components over a network
US8856600B2 (en) * 2012-06-21 2014-10-07 Breakingpoint Systems, Inc. JTAG-based programming and debug
US8645779B2 (en) 2012-06-21 2014-02-04 Freescale Semiconductor, Inc. Scan testing of integrated circuits and on-chip modules
US9026688B2 (en) 2012-06-21 2015-05-05 Breakingpoint Systems, Inc. Systems and methods for programming configurable logic devices via USB
CN105354136B (en) 2015-09-25 2018-06-15 华为技术有限公司 A kind of adjustment method, multi-core processor and commissioning device
CN105224454B (en) 2015-09-25 2018-06-05 华为技术有限公司 A kind of adjustment method, polycaryon processor and commissioning device
US20180338284A1 (en) * 2017-05-18 2018-11-22 Qualcomm Incorporated Resource utilization for reduced user equipment power consumption
RU2703493C1 (en) * 2018-12-28 2019-10-17 федеральное государственное автономное образовательное учреждение высшего образования "Самарский национальный исследовательский университет имени академика С.П. Королёва" Method of localization of short-circuit faults of outputs of microcircuit chips jtag by interface and device for its implementation
CN110083560A (en) * 2019-04-03 2019-08-02 杭州迪普科技股份有限公司 A kind of more jtag interfaces switching chip, method and debugging single board system
DE112019007386T5 (en) 2019-05-31 2022-02-17 Micron Technology, Inc. IMPROVED JTAG REGISTERS WITH SIMULTANEOUS INPUTS

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US5448576A (en) * 1992-10-29 1995-09-05 Bull Hn Information Systems Inc. Boundary scan architecture extension
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US5581101A (en) 1995-01-03 1996-12-03 International Business Machines Corporation FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures
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US5909453A (en) * 1997-07-02 1999-06-01 Xilinx, Inc. Lookahead structure for fast scan testing
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US6289300B1 (en) * 1998-02-06 2001-09-11 Analog Devices, Inc. Integrated circuit with embedded emulator and emulation system for use with such an integrated circuit
US6230119B1 (en) * 1998-02-06 2001-05-08 Patrick Michael Mitchell Integrated circuit with embedded emulator and emulation system for use with such an integrated circuit
US6381717B1 (en) * 1998-04-24 2002-04-30 Texas Instruments Incorporated Snoopy test access port architecture for electronic circuits including embedded core having test access port with instruction driven wake-up
US6389565B2 (en) * 1998-05-29 2002-05-14 Agilent Technologies, Inc. Mechanism and display for boundary-scan debugging information
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US6611796B1 (en) * 1999-10-20 2003-08-26 Texas Instruments Incorporated Method and apparatus for combining memory blocks for in circuit emulation
US6859897B2 (en) * 2000-03-02 2005-02-22 Texas Instruments Incorporated Range based detection of memory access
US6931636B2 (en) * 2000-08-08 2005-08-16 Texas Instruments Incorporated Multiprocessor emulation support using dynamic linking
US6886110B2 (en) * 2000-11-21 2005-04-26 Wind River Systems, Inc. Multiple device scan chain emulation/debugging
US6691251B2 (en) * 2000-11-30 2004-02-10 Palmsource, Inc. On-chip debugging system emulator
US6954887B2 (en) * 2001-03-22 2005-10-11 Syntest Technologies, Inc. Multiple-capture DFT system for scan-based integrated circuits
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US7047462B2 (en) * 2002-01-04 2006-05-16 Hewlett-Packard Development Company, Lp. Method and apparatus for providing JTAG functionality in a remote server management controller
US20030163773A1 (en) * 2002-02-26 2003-08-28 O'brien James J. Multi-core controller
US20030233221A1 (en) * 2002-06-03 2003-12-18 O'brien James J. JTAG server and sequence accelerator for multicore applications
US20030225566A1 (en) * 2002-06-03 2003-12-04 O'brein James J. JTAG server
US7131033B1 (en) * 2002-06-21 2006-10-31 Cypress Semiconductor Corp. Substrate configurable JTAG ID scheme
US7053470B1 (en) * 2005-02-19 2006-05-30 Azul Systems, Inc. Multi-chip package having repairable embedded memories on a system chip with an EEPROM chip storing repair information
US7747901B2 (en) * 2005-07-20 2010-06-29 Texas Instruments Incorporated Auxiliary link control commands

Also Published As

Publication number Publication date
US6886110B2 (en) 2005-04-26
WO2002042949A1 (en) 2002-05-30
US7707022B2 (en) 2010-04-27
US20060195739A1 (en) 2006-08-31
US20020099531A1 (en) 2002-07-25

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