AU2002225743A1 - Method and apparatus for synchronizing interrupts in a message passing queue oriented bus system - Google Patents

Method and apparatus for synchronizing interrupts in a message passing queue oriented bus system

Info

Publication number
AU2002225743A1
AU2002225743A1 AU2002225743A AU2574302A AU2002225743A1 AU 2002225743 A1 AU2002225743 A1 AU 2002225743A1 AU 2002225743 A AU2002225743 A AU 2002225743A AU 2574302 A AU2574302 A AU 2574302A AU 2002225743 A1 AU2002225743 A1 AU 2002225743A1
Authority
AU
Australia
Prior art keywords
bus system
message passing
oriented bus
passing queue
interrupts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002225743A
Inventor
James M. Avery
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of AU2002225743A1 publication Critical patent/AU2002225743A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
AU2002225743A 2000-11-16 2001-11-16 Method and apparatus for synchronizing interrupts in a message passing queue oriented bus system Abandoned AU2002225743A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09/713,913 US6622193B1 (en) 2000-11-16 2000-11-16 Method and apparatus for synchronizing interrupts in a message passing queue oriented bus system
US09/713,913 2000-11-16
US09713913 2000-11-16
PCT/US2001/044131 WO2002041156A2 (en) 2000-11-16 2001-11-16 Method and apparatus for synchronizing interrupts in a message passing queue oriented bus system

Publications (1)

Publication Number Publication Date
AU2002225743A1 true AU2002225743A1 (en) 2002-05-27

Family

ID=24868047

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002225743A Abandoned AU2002225743A1 (en) 2000-11-16 2001-11-16 Method and apparatus for synchronizing interrupts in a message passing queue oriented bus system

Country Status (4)

Country Link
US (1) US6622193B1 (en)
AU (1) AU2002225743A1 (en)
GB (1) GB2384896B (en)
WO (1) WO2002041156A2 (en)

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US20020159456A1 (en) * 2001-04-27 2002-10-31 Foster Michael S. Method and system for multicasting in a routing device
US6885673B1 (en) * 2001-05-21 2005-04-26 Advanced Micro Devices, Inc. Queue pair wait state management in a host channel adapter
US7346707B1 (en) * 2002-01-16 2008-03-18 Advanced Micro Devices, Inc. Arrangement in an infiniband channel adapter for sharing memory space for work queue entries using multiply-linked lists
WO2004046926A1 (en) * 2002-11-21 2004-06-03 Fujitsu Limited Method, device and processor system for notifying event
US7512695B2 (en) * 2003-05-07 2009-03-31 Avago Technologies General Ip (Singapore) Pte. Ltd. Method and system to control the communication of data between a plurality of interconnect devices
US7234037B2 (en) * 2003-11-25 2007-06-19 International Business Machines Corporation Memory mapped Input/Output operations
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JP4731126B2 (en) * 2004-03-30 2011-07-20 ルネサスエレクトロニクス株式会社 Interrupt control circuit
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US7480298B2 (en) * 2004-08-30 2009-01-20 International Business Machines Corporation Lazy deregistration of user virtual machine to adapter protocol virtual offsets
US20060069818A1 (en) * 2004-09-27 2006-03-30 Cliff Mather Synchronizing direct memory access and evacuation operations in a computer system
US20060095690A1 (en) * 2004-10-29 2006-05-04 International Business Machines Corporation System, method, and storage medium for shared key index space for memory regions
US7260663B2 (en) 2005-04-07 2007-08-21 International Business Machines Corporation System and method for presenting interrupts
US7581021B2 (en) * 2005-04-07 2009-08-25 International Business Machines Corporation System and method for providing multiple virtual host channel adapters using virtual switches
US7290077B2 (en) * 2005-04-07 2007-10-30 International Business Machines Corporation Event queue structure and method
US7200704B2 (en) * 2005-04-07 2007-04-03 International Business Machines Corporation Virtualization of an I/O adapter port using enablement and activation functions
US10225282B2 (en) 2005-04-14 2019-03-05 International Business Machines Corporation System, method and program product to identify a distributed denial of service attack
US7480784B2 (en) * 2005-08-12 2009-01-20 Advanced Micro Devices, Inc. Ensuring deadlock free operation for peer to peer traffic in an input/output memory management unit (IOMMU)
US7516247B2 (en) 2005-08-12 2009-04-07 Advanced Micro Devices, Inc. Avoiding silent data corruption and data leakage in a virtual environment with multiple guests
US7793067B2 (en) * 2005-08-12 2010-09-07 Globalfoundries Inc. Translation data prefetch in an IOMMU
US7543131B2 (en) * 2005-08-12 2009-06-02 Advanced Micro Devices, Inc. Controlling an I/O MMU
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US8650342B2 (en) * 2006-10-23 2014-02-11 Dell Products L.P. System and method for distributed address translation in virtualized information handling systems
US7849287B2 (en) * 2006-11-13 2010-12-07 Advanced Micro Devices, Inc. Efficiently controlling special memory mapped system accesses
US7873770B2 (en) * 2006-11-13 2011-01-18 Globalfoundries Inc. Filtering and remapping interrupts
US8169968B1 (en) * 2007-05-10 2012-05-01 Rockstar Consortium Reducing communication silence when performing inter-technology handoff
US8402190B2 (en) * 2008-12-02 2013-03-19 International Business Machines Corporation Network adaptor optimization and interrupt reduction
US8234432B2 (en) * 2009-01-26 2012-07-31 Advanced Micro Devices, Inc. Memory structure to store interrupt state for inactive guests
US8302109B2 (en) * 2009-02-24 2012-10-30 International Business Machines Corporation Synchronization optimized queuing system
US8032686B2 (en) * 2009-04-30 2011-10-04 Oracle America, Inc. Protocol translation in a data storage system
US8489789B2 (en) * 2010-02-05 2013-07-16 Advanced Micro Devices, Inc. Interrupt virtualization
US8644139B2 (en) * 2010-04-26 2014-02-04 International Business Machines Corporation Priority based flow control within a virtual distributed bridge environment
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US9355031B2 (en) * 2011-04-21 2016-05-31 International Business Machines Corporation Techniques for mapping device addresses to physical memory addresses
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Also Published As

Publication number Publication date
WO2002041156A3 (en) 2002-07-18
US6622193B1 (en) 2003-09-16
WO2002041156A2 (en) 2002-05-23
GB2384896A (en) 2003-08-06
GB0310607D0 (en) 2003-06-11
GB2384896B (en) 2005-02-09

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