AU2002224850A1 - Power management method and arrangement for bus-coupled circuit blocks - Google Patents

Power management method and arrangement for bus-coupled circuit blocks

Info

Publication number
AU2002224850A1
AU2002224850A1 AU2002224850A AU2485002A AU2002224850A1 AU 2002224850 A1 AU2002224850 A1 AU 2002224850A1 AU 2002224850 A AU2002224850 A AU 2002224850A AU 2485002 A AU2485002 A AU 2485002A AU 2002224850 A1 AU2002224850 A1 AU 2002224850A1
Authority
AU
Australia
Prior art keywords
circuit block
bus
clocked
accessing
circuit blocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002224850A
Inventor
Rajeev Sethia
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of AU2002224850A1 publication Critical patent/AU2002224850A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A power management system permits power-reduced operation of selected circuit blocks in a manner that requires no modification to other bus-coupled circuit blocks attempting to communicate with such selected circuit blocks. Consistent with one embodiment of the present invention, the approach is implemented in a digital electronic circuit arrangement having an accessing circuit block coupled to a clocked circuit block over a data bus. The clocked circuit block is power managed by decreasing, e.g., reducing or blocking, the clock speed to the clocked circuit block which impedes its ability communicate over the data bus. Once the clocked circuit block is set in a reduced power mode, the bus is monitored for data-access communications from the accessing circuit block to the clocked circuit block. In response to such a communication, a substitute response is generated on the data bus, directed to the accessing circuit block, and the clock speed to the clocked circuit block, is increased and brought out of the reduced power mode for further communications with the accessing circuit block.
AU2002224850A 2000-11-15 2001-11-13 Power management method and arrangement for bus-coupled circuit blocks Abandoned AU2002224850A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/713,073 US6694441B1 (en) 2000-11-15 2000-11-15 Power management method and arrangement for bus-coupled circuit blocks
US09/713,073 2000-11-15
PCT/EP2001/013187 WO2002041124A2 (en) 2000-11-15 2001-11-13 Power management method and arrangement for bus-coupled circuit blocks

Publications (1)

Publication Number Publication Date
AU2002224850A1 true AU2002224850A1 (en) 2002-05-27

Family

ID=24864632

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002224850A Abandoned AU2002224850A1 (en) 2000-11-15 2001-11-13 Power management method and arrangement for bus-coupled circuit blocks

Country Status (9)

Country Link
US (1) US6694441B1 (en)
EP (1) EP1337908B1 (en)
JP (1) JP4202754B2 (en)
KR (1) KR100895543B1 (en)
CN (1) CN1269001C (en)
AT (1) ATE472130T1 (en)
AU (1) AU2002224850A1 (en)
DE (1) DE60142443D1 (en)
WO (1) WO2002041124A2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6859886B1 (en) * 2001-10-02 2005-02-22 Lsi Logic Corporation IO based embedded processor clock speed control
EP1550229B1 (en) * 2002-10-10 2017-03-15 Symbol Technologies, LLC Wlan communications system
US7400912B2 (en) 2002-10-10 2008-07-15 Symbol Technologies, Inc. Wlan communications system
KR100630693B1 (en) 2004-07-28 2006-10-02 삼성전자주식회사 Bus arbitration system and method improving power consumption
US7656237B2 (en) * 2004-12-02 2010-02-02 International Business Machines Corporation Method to gate off PLLS in a deep power saving state without separate clock distribution for power management logic
US7284138B2 (en) * 2004-12-02 2007-10-16 International Business Machines Corporation Deep power saving by disabling clock distribution without separate clock distribution for power management logic
US7616036B1 (en) 2005-09-12 2009-11-10 Virage Logic Corporation Programmable strobe and clock generator
US7519888B2 (en) * 2005-09-12 2009-04-14 Virage Logic Corporation Input-output device testing
GB0908882D0 (en) * 2009-05-22 2009-07-01 Zarlink Semiconductor Inc Digital/analog phase locked loop
CN102301357B (en) * 2011-07-08 2015-03-11 华为技术有限公司 Method for switching work clock, intelligent gating circuit and system
KR101842245B1 (en) * 2011-07-25 2018-03-26 삼성전자주식회사 Bus system in SoC and method of gating root clocks therefor
GB201211340D0 (en) * 2012-06-26 2012-08-08 Nordic Semiconductor Asa Control of semiconductor devices
JP2015176214A (en) * 2014-03-13 2015-10-05 株式会社東芝 Communication apparatus
KR101883784B1 (en) * 2018-03-20 2018-07-31 삼성전자주식회사 Bus system in SoC and method of gating root clocks therefor

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2229024B (en) 1989-03-06 1992-12-02 Creda Ltd Controlling remote electrical appliances via the mains supply
US5345564A (en) 1992-03-31 1994-09-06 Zilog, Inc. Serial communication peripheral integrated electronic circuit that recognizes its unique address before the entire circuit is enabled
US5392437A (en) * 1992-11-06 1995-02-21 Intel Corporation Method and apparatus for independently stopping and restarting functional units
US5483656A (en) * 1993-01-14 1996-01-09 Apple Computer, Inc. System for managing power consumption of devices coupled to a common bus
ATE231254T1 (en) * 1994-04-28 2003-02-15 Advanced Micro Devices Inc SYSTEM FOR CONTROLLING A PERIPHERAL BUST CLOCK SIGNAL
EP0809825A1 (en) 1995-02-14 1997-12-03 Vlsi Technology, Inc. Method and apparatus for reducing power consumption in digital electronic circuits
US5652895A (en) * 1995-12-26 1997-07-29 Intel Corporation Computer system having a power conservation mode and utilizing a bus arbiter device which is operable to control the power conservation mode
US5987620A (en) * 1997-09-19 1999-11-16 Thang Tran Method and apparatus for a self-timed and self-enabled distributed clock
US6154803A (en) 1998-12-18 2000-11-28 Philips Semiconductors, Inc. Method and arrangement for passing data between a reference chip and an external bus

Also Published As

Publication number Publication date
EP1337908A2 (en) 2003-08-27
JP4202754B2 (en) 2008-12-24
WO2002041124A2 (en) 2002-05-23
CN1269001C (en) 2006-08-09
KR20020063626A (en) 2002-08-03
EP1337908B1 (en) 2010-06-23
US6694441B1 (en) 2004-02-17
WO2002041124A3 (en) 2003-03-13
CN1471664A (en) 2004-01-28
DE60142443D1 (en) 2010-08-05
ATE472130T1 (en) 2010-07-15
JP2004514211A (en) 2004-05-13
KR100895543B1 (en) 2009-04-29

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