AU2002220203A1 - Clock extraction from a biphase encoded bit stream - Google Patents

Clock extraction from a biphase encoded bit stream

Info

Publication number
AU2002220203A1
AU2002220203A1 AU2002220203A AU2020302A AU2002220203A1 AU 2002220203 A1 AU2002220203 A1 AU 2002220203A1 AU 2002220203 A AU2002220203 A AU 2002220203A AU 2020302 A AU2020302 A AU 2020302A AU 2002220203 A1 AU2002220203 A1 AU 2002220203A1
Authority
AU
Australia
Prior art keywords
bit stream
encoded bit
clock extraction
biphase encoded
biphase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002220203A
Inventor
Sanjay Ramakrishna Pillay
Hasibur Rahman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cirrus Logic Inc
Original Assignee
Cirrus Logic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cirrus Logic Inc filed Critical Cirrus Logic Inc
Publication of AU2002220203A1 publication Critical patent/AU2002220203A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
    • H04H20/86—Arrangements characterised by the broadcast information itself
    • H04H20/95—Arrangements characterised by the broadcast information itself characterised by a specific format, e.g. an encoded audio stream
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Dc Digital Transmission (AREA)
AU2002220203A 2000-12-05 2001-11-07 Clock extraction from a biphase encoded bit stream Abandoned AU2002220203A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/730,284 US6782300B2 (en) 2000-12-05 2000-12-05 Circuits and methods for extracting a clock from a biphase encoded bit stream and systems using the same
US09/730,284 2000-12-05
PCT/US2001/046456 WO2002047341A1 (en) 2000-12-05 2001-11-07 Clock extraction from a biphase encoded bit stream

Publications (1)

Publication Number Publication Date
AU2002220203A1 true AU2002220203A1 (en) 2002-06-18

Family

ID=24934701

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002220203A Abandoned AU2002220203A1 (en) 2000-12-05 2001-11-07 Clock extraction from a biphase encoded bit stream

Country Status (3)

Country Link
US (1) US6782300B2 (en)
AU (1) AU2002220203A1 (en)
WO (1) WO2002047341A1 (en)

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US7180966B2 (en) * 2001-10-26 2007-02-20 International Business Machines Corporation Transition detection, validation and memorization circuit
US20030217301A1 (en) * 2002-05-16 2003-11-20 Levy Paul S. Method and apparatus for transmitting side-band data within a source synchronous clock signal
JP4554361B2 (en) * 2002-06-21 2010-09-29 トムソン ライセンシング Broadcast router with serial digital audio data stream decoder
US7664214B2 (en) * 2002-09-24 2010-02-16 Standard Microsystems Corporation System and method for transferring data among transceivers substantially void of data dependent jitter
US7978800B2 (en) * 2002-10-10 2011-07-12 Finisar Corporation Circuit for converting a transponder controller chip output into an appropriate input signal for a host device
KR100460207B1 (en) * 2002-10-16 2004-12-08 학교법인 포항공과대학교 Look ahead decision feedback equalizing receiver
US20040096025A1 (en) * 2002-11-20 2004-05-20 Rupp Michael E. Method and system for a programmable diphase digital phase lock loop
US7440515B2 (en) * 2004-10-25 2008-10-21 Atmel Corporation System and method for controlling modulation
US7599388B2 (en) * 2005-03-29 2009-10-06 Echo Digital Audio Corporation System and method for high-bandwidth serial bus data transfer
KR101225082B1 (en) * 2006-01-17 2013-01-22 삼성전자주식회사 Apparatus and method for transmitting/receiving uncompressed AV data
WO2007125472A2 (en) * 2006-04-28 2007-11-08 Nxp B.V. Data processing apparatus
US7702005B2 (en) * 2006-08-17 2010-04-20 Alpha Imaging Technology Corp. Method for transmitting and/or receiving audio data of a plurality of audio sources through a single SPDIF link, and related apparatus
TWI324320B (en) * 2006-09-01 2010-05-01 Ind Tech Res Inst Rfid tag system and data stream thereof
TWI320908B (en) * 2006-10-27 2010-02-21 Ind Tech Res Inst Apparatus and method for increasing the utilization by the processors on the shared resources
US20090323880A1 (en) * 2008-06-27 2009-12-31 Microsoft Corporation Synchronization of real time data within deterministic clock edge
US8350734B1 (en) 2008-12-10 2013-01-08 Ess Technology, Inc. Method and apparatus for digital to analog conversion of data stream with random and low-frequency periodic jitter
US9014305B2 (en) 2011-06-23 2015-04-21 Texas Instruments Incorporated Bi-phase communication demodulation techniques
WO2014066707A2 (en) 2012-10-26 2014-05-01 Mediatek Singapore Pte. Ltd. Wireless power transfer in-band communication system
US10411831B2 (en) 2012-10-26 2019-09-10 Mediatek Singapore Pte. Ltd. Wireless power transfer in-band communication system
KR101418339B1 (en) * 2012-12-03 2014-07-16 한국표준과학연구원 Apparatus of Digital-data Transmission for Controling Multi-channel SQUID System
US10277385B1 (en) 2018-05-27 2019-04-30 Nxp B.V. Slave node for CAN bus network
CN115940952B (en) * 2023-01-05 2023-05-26 南京芯驰半导体科技有限公司 ATE test method and device for digital-to-analog converter chip, electronic equipment and medium

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3632719A1 (en) 1986-09-26 1988-03-31 Grundig Emv Circuit for regenerating the clock signal in a signal transmitted in biphase code
GB2243269B (en) 1990-04-19 1994-04-13 British Broadcasting Corp Decoding binary-coded transmissions
US5465268A (en) 1994-01-14 1995-11-07 The Grass Valley Group, Inc. Digital decoding of biphase-mark encoded serial digital signals
US5889820A (en) 1996-10-08 1999-03-30 Analog Devices, Inc. SPDIF-AES/EBU digital audio data recovery
US6249555B1 (en) * 1997-07-14 2001-06-19 Grass Valley (Us) Inc. Low jitter digital extraction of data from serial bitstreams
DE69724631D1 (en) 1997-12-04 2003-10-09 St Microelectronics Srl Decoding of a biphase modulated bit stream and self-synchronizing frequency divider with non-integer ratio
DE19932692A1 (en) * 1999-07-15 2001-01-18 Patent Treuhand Ges Fuer Elektrische Gluehlampen Mbh Method for sampling biphase encoded digital signals

Also Published As

Publication number Publication date
US6782300B2 (en) 2004-08-24
WO2002047341A8 (en) 2002-09-26
US20030195645A1 (en) 2003-10-16
WO2002047341A1 (en) 2002-06-13

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