AU2001294013A1 - System, method and article of manufacture for data transfer across clock domains - Google Patents
System, method and article of manufacture for data transfer across clock domainsInfo
- Publication number
- AU2001294013A1 AU2001294013A1 AU2001294013A AU9401301A AU2001294013A1 AU 2001294013 A1 AU2001294013 A1 AU 2001294013A1 AU 2001294013 A AU2001294013 A AU 2001294013A AU 9401301 A AU9401301 A AU 9401301A AU 2001294013 A1 AU2001294013 A1 AU 2001294013A1
- Authority
- AU
- Australia
- Prior art keywords
- article
- manufacture
- data transfer
- clock domains
- domains
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Stored Programmes (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US68741900A | 2000-10-12 | 2000-10-12 | |
US09/687,419 | 2000-10-12 | ||
US09/772,521 | 2001-01-29 | ||
US09/772,521 US20020069375A1 (en) | 2000-10-12 | 2001-01-29 | System, method, and article of manufacture for data transfer across clock domains |
PCT/GB2001/004538 WO2002031664A2 (en) | 2000-10-12 | 2001-10-11 | System, method and article of manufacture for data transfer across clock domains |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2001294013A1 true AU2001294013A1 (en) | 2002-04-22 |
Family
ID=27104006
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2001294013A Abandoned AU2001294013A1 (en) | 2000-10-12 | 2001-10-11 | System, method and article of manufacture for data transfer across clock domains |
Country Status (3)
Country | Link |
---|---|
US (1) | US20020069375A1 (en) |
AU (1) | AU2001294013A1 (en) |
WO (1) | WO2002031664A2 (en) |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3502592B2 (en) * | 2000-03-02 | 2004-03-02 | 株式会社東芝 | Branch prediction device |
US7139743B2 (en) | 2000-04-07 | 2006-11-21 | Washington University | Associative database scanning and information retrieval using FPGA devices |
WO2003026175A2 (en) * | 2001-08-31 | 2003-03-27 | Siemens Aktiengesellschaft | Transmission of large volumes of data via asynchronous interfaces in circuits with redundancy concept of the checker-master type |
US7257810B2 (en) * | 2001-11-02 | 2007-08-14 | Sun Microsystems, Inc. | Method and apparatus for inserting prefetch instructions in an optimizing compiler |
US7234136B2 (en) * | 2001-11-02 | 2007-06-19 | Sun Microsystems, Inc. | Method and apparatus for selecting references for prefetching in an optimizing compiler |
US7130890B1 (en) * | 2002-09-04 | 2006-10-31 | Hewlett-Packard Development Company, L.P. | Method and system for adaptively prefetching objects from a network |
FR2849228A1 (en) * | 2002-12-23 | 2004-06-25 | St Microelectronics Sa | Data transfer device for linking two asynchronous systems communicating via a FIFO buffer memory, each system having a pointing register with associated primary and secondary phantom registers |
US7472199B1 (en) | 2003-03-28 | 2008-12-30 | Qualcomm Incorporated | System and method for receiving data at a first rate and adapting the data for being transported at a second rate |
CA2522862A1 (en) | 2003-05-23 | 2005-03-24 | Washington University | Intelligent data storage and processing using fpga devices |
US10572824B2 (en) | 2003-05-23 | 2020-02-25 | Ip Reservoir, Llc | System and method for low latency multi-functional pipeline with correlation logic and selectively activated/deactivated pipelined data processing engines |
US20070038782A1 (en) * | 2005-07-26 | 2007-02-15 | Ambric, Inc. | System of virtual data channels across clock boundaries in an integrated circuit |
US7801033B2 (en) * | 2005-07-26 | 2010-09-21 | Nethra Imaging, Inc. | System of virtual data channels in an integrated circuit |
US7412678B2 (en) * | 2004-06-02 | 2008-08-12 | Lsi Corporation | Method and computer program for management of synchronous and asynchronous clock domain crossing in integrated circuit design |
US7624209B1 (en) * | 2004-09-15 | 2009-11-24 | Xilinx, Inc. | Method of and circuit for enabling variable latency data transfers |
MY137746A (en) * | 2004-12-06 | 2009-03-31 | Intel Corp | System, apparatus, and method to increase information transfer across clock domains |
EP1859378A2 (en) | 2005-03-03 | 2007-11-28 | Washington University | Method and apparatus for performing biosequence similarity searching |
US7921046B2 (en) | 2006-06-19 | 2011-04-05 | Exegy Incorporated | High speed processing of financial information using FPGA devices |
US7840482B2 (en) | 2006-06-19 | 2010-11-23 | Exegy Incorporated | Method and system for high speed options pricing |
US8326819B2 (en) | 2006-11-13 | 2012-12-04 | Exegy Incorporated | Method and system for high performance data metatagging and data indexing using coprocessors |
US10229453B2 (en) | 2008-01-11 | 2019-03-12 | Ip Reservoir, Llc | Method and system for low latency basket calculation |
US7925871B2 (en) * | 2008-02-19 | 2011-04-12 | Arm Limited | Identification and correction of cyclically recurring errors in one or more branch predictors |
US20120095893A1 (en) | 2008-12-15 | 2012-04-19 | Exegy Incorporated | Method and apparatus for high-speed processing of financial market depth data |
US20100322365A1 (en) * | 2009-06-18 | 2010-12-23 | Technion Research And Development Foundation Ltd. | System and method for synchronizing multi-clock domains |
US8838544B2 (en) * | 2009-09-23 | 2014-09-16 | International Business Machines Corporation | Fast history based compression in a pipelined architecture |
US8583894B2 (en) * | 2010-09-09 | 2013-11-12 | Advanced Micro Devices | Hybrid prefetch method and apparatus |
WO2012079041A1 (en) | 2010-12-09 | 2012-06-14 | Exegy Incorporated | Method and apparatus for managing orders in financial markets |
US9047243B2 (en) | 2011-12-14 | 2015-06-02 | Ip Reservoir, Llc | Method and apparatus for low latency data distribution |
US9990393B2 (en) | 2012-03-27 | 2018-06-05 | Ip Reservoir, Llc | Intelligent feed switch |
US10650452B2 (en) | 2012-03-27 | 2020-05-12 | Ip Reservoir, Llc | Offload processing of data packets |
US10121196B2 (en) | 2012-03-27 | 2018-11-06 | Ip Reservoir, Llc | Offload processing of data packets containing financial market data |
US11436672B2 (en) | 2012-03-27 | 2022-09-06 | Exegy Incorporated | Intelligent switch for processing financial market data |
WO2018119035A1 (en) | 2016-12-22 | 2018-06-28 | Ip Reservoir, Llc | Pipelines for hardware-accelerated machine learning |
GB2572780B (en) * | 2018-04-10 | 2020-07-15 | Advanced Risc Mach Ltd | An Apparatus and Method for Controlling Allocation Of Instructions Into An Instruction Cache Storage |
CN113626376B (en) * | 2021-04-30 | 2023-08-18 | 中国电子科技集团公司第十四研究所 | FPGA-based software real-time dynamic reconfigurable control method and system |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2262415B (en) * | 1991-12-13 | 1995-08-16 | Digital Equipment Int | Handshake synchronization system |
-
2001
- 2001-01-29 US US09/772,521 patent/US20020069375A1/en not_active Abandoned
- 2001-10-11 AU AU2001294013A patent/AU2001294013A1/en not_active Abandoned
- 2001-10-11 WO PCT/GB2001/004538 patent/WO2002031664A2/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
US20020069375A1 (en) | 2002-06-06 |
WO2002031664A3 (en) | 2003-05-01 |
WO2002031664A2 (en) | 2002-04-18 |
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