AU2001291264A1 - Apparatus and method for using tagged pointers for extract, insert and format operations - Google Patents

Apparatus and method for using tagged pointers for extract, insert and format operations

Info

Publication number
AU2001291264A1
AU2001291264A1 AU2001291264A AU9126401A AU2001291264A1 AU 2001291264 A1 AU2001291264 A1 AU 2001291264A1 AU 2001291264 A AU2001291264 A AU 2001291264A AU 9126401 A AU9126401 A AU 9126401A AU 2001291264 A1 AU2001291264 A1 AU 2001291264A1
Authority
AU
Australia
Prior art keywords
extract
insert
format operations
pointers
tagged
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001291264A
Inventor
John L. Redford
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ChipWrights Design Inc
Original Assignee
ChipWrights Design Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ChipWrights Design Inc filed Critical ChipWrights Design Inc
Publication of AU2001291264A1 publication Critical patent/AU2001291264A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30192—Instruction operation extension or modification according to data descriptor, e.g. dynamic data typing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Document Processing Apparatus (AREA)
  • Devices For Executing Special Programs (AREA)
AU2001291264A 2000-08-23 2001-08-20 Apparatus and method for using tagged pointers for extract, insert and format operations Abandoned AU2001291264A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/644,633 2000-08-23
US09/644,633 US6678806B1 (en) 2000-08-23 2000-08-23 Apparatus and method for using tagged pointers for extract, insert and format operations
PCT/US2001/041791 WO2002017072A2 (en) 2000-08-23 2001-08-20 Apparatus and method for using tagged pointers for extract, insert and format operations

Publications (1)

Publication Number Publication Date
AU2001291264A1 true AU2001291264A1 (en) 2002-03-04

Family

ID=24585733

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001291264A Abandoned AU2001291264A1 (en) 2000-08-23 2001-08-20 Apparatus and method for using tagged pointers for extract, insert and format operations

Country Status (5)

Country Link
US (1) US6678806B1 (en)
EP (1) EP1410175A2 (en)
AU (1) AU2001291264A1 (en)
TW (1) TW530259B (en)
WO (1) WO2002017072A2 (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2485774A (en) 2010-11-23 2012-05-30 Advanced Risc Mach Ltd Processor instruction to extract a bit field from one operand and insert it into another with an option to sign or zero extend the field
GB2488985A (en) * 2011-03-08 2012-09-19 Advanced Risc Mach Ltd Mixed size data processing operation with integrated operand conversion instructions
EP2727114B1 (en) 2011-06-28 2020-04-22 Hewlett-Packard Enterprise Development LP Shiftable memory
WO2013062561A1 (en) 2011-10-27 2013-05-02 Hewlett-Packard Development Company, L.P. Shiftable memory supporting atomic operation
KR101660611B1 (en) 2012-01-30 2016-09-27 휴렛 팩커드 엔터프라이즈 디벨롭먼트 엘피 Word shift static random access memory(ws-sram)
US9431074B2 (en) 2012-03-02 2016-08-30 Hewlett Packard Enterprise Development Lp Shiftable memory supporting bimodal storage
WO2013130109A1 (en) 2012-03-02 2013-09-06 Hewlett-Packard Development Company L.P. Shiftable memory defragmentation
BR112017023452B1 (en) * 2015-07-31 2022-12-20 Hewlett-Packard Development Company, L.P. APPARATUS COMPRISING IMAGING SUPPLIES
US10409614B2 (en) 2017-04-24 2019-09-10 Intel Corporation Instructions having support for floating point and integer data types in the same register
US10474458B2 (en) 2017-04-28 2019-11-12 Intel Corporation Instructions and logic to perform floating-point and integer operations for machine learning
US11934342B2 (en) 2019-03-15 2024-03-19 Intel Corporation Assistance for hardware prefetch in cache access
EP4024223A1 (en) 2019-03-15 2022-07-06 Intel Corporation Systems and methods for cache optimization
AU2020241262A1 (en) 2019-03-15 2021-11-04 Intel Corporation Sparse optimizations for a matrix accelerator architecture
US12013808B2 (en) 2019-03-15 2024-06-18 Intel Corporation Multi-tile architecture for graphics operations

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4138720A (en) * 1977-04-04 1979-02-06 Burroughs Corporation Time-shared, multi-phase memory accessing system
SE424581B (en) * 1981-08-21 1982-07-26 Ibm Svenska Ab METHOD AND DEVICE FOR ADDRESSING A MEMORY
US4604695A (en) 1983-09-30 1986-08-05 Honeywell Information Systems Inc. Nibble and word addressable memory arrangement
EP0148478B1 (en) 1983-12-23 1989-08-09 Hitachi, Ltd. A data processor with control of the significant bit lenghts of general purpose registers
US4896258A (en) 1985-07-04 1990-01-23 Hitachi, Ltd. Data processor provided with instructions which refer to both tagged and tagless data
US5224214A (en) * 1990-04-12 1993-06-29 Digital Equipment Corp. BuIffet for gathering write requests and resolving read conflicts by matching read and write requests
JPH0756892A (en) * 1993-08-10 1995-03-03 Fujitsu Ltd Computer having vector arithmetic unit with mask
US5590352A (en) 1994-04-26 1996-12-31 Advanced Micro Devices, Inc. Dependency checking and forwarding of variable width operands
US6292879B1 (en) 1995-10-25 2001-09-18 Anthony S. Fong Method and apparatus to specify access control list and cache enabling and cache coherency requirement enabling on individual operands of an instruction of a computer
JPH11272546A (en) 1998-03-23 1999-10-08 Nec Corp Variable length register device
US6282623B1 (en) * 2000-02-04 2001-08-28 Motorola Inc. Method for digital signal processing, DSP, mobile communication and audi o-device

Also Published As

Publication number Publication date
TW530259B (en) 2003-05-01
EP1410175A2 (en) 2004-04-21
WO2002017072A2 (en) 2002-02-28
WO2002017072A3 (en) 2002-10-17
US6678806B1 (en) 2004-01-13

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