AU2001290461A1 - A pipelined microprocessor and a method relating thereto - Google Patents

A pipelined microprocessor and a method relating thereto

Info

Publication number
AU2001290461A1
AU2001290461A1 AU2001290461A AU9046101A AU2001290461A1 AU 2001290461 A1 AU2001290461 A1 AU 2001290461A1 AU 2001290461 A AU2001290461 A AU 2001290461A AU 9046101 A AU9046101 A AU 9046101A AU 2001290461 A1 AU2001290461 A1 AU 2001290461A1
Authority
AU
Australia
Prior art keywords
method relating
pipelined microprocessor
pipelined
microprocessor
relating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001290461A
Inventor
Magnus Carlsson
Joachim Strombergson
Jonas Vasell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Publication of AU2001290461A1 publication Critical patent/AU2001290461A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30079—Pipeline control instructions, e.g. multicycle NOP
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
AU2001290461A 2000-09-27 2001-09-26 A pipelined microprocessor and a method relating thereto Abandoned AU2001290461A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE0003446 2000-09-27
SE0003446A SE0003446L (en) 2000-09-27 2000-09-27 A pipeline microprocessor and a method related thereto
PCT/SE2001/002066 WO2002027480A1 (en) 2000-09-27 2001-09-26 A pipelined microprocessor and a method relating thereto

Publications (1)

Publication Number Publication Date
AU2001290461A1 true AU2001290461A1 (en) 2002-04-08

Family

ID=20281172

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001290461A Abandoned AU2001290461A1 (en) 2000-09-27 2001-09-26 A pipelined microprocessor and a method relating thereto

Country Status (5)

Country Link
US (1) US6807621B2 (en)
EP (1) EP1323033B1 (en)
AU (1) AU2001290461A1 (en)
SE (1) SE0003446L (en)
WO (1) WO2002027480A1 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3900485B2 (en) * 2002-07-29 2007-04-04 インターナショナル・ビジネス・マシーンズ・コーポレーション Optimization device, compiler program, optimization method, and recording medium
US20050050303A1 (en) * 2003-06-30 2005-03-03 Roni Rosner Hierarchical reorder buffers for controlling speculative execution in a multi-cluster system
US7478402B2 (en) * 2004-02-12 2009-01-13 Microsoft Corporation Configurable message pipelines
US7278014B2 (en) * 2004-12-02 2007-10-02 International Business Machines Corporation System and method for simulating hardware interrupts
US7617387B2 (en) * 2006-09-27 2009-11-10 Qualcomm Incorporated Methods and system for resolving simultaneous predicted branch instructions
US7984279B2 (en) * 2006-11-03 2011-07-19 Qualcomm Incorporated System and method for using a working global history register
US9928128B2 (en) 2016-04-01 2018-03-27 International Business Machines Corporation In-pipe error scrubbing within a processor core
US10761854B2 (en) * 2016-04-19 2020-09-01 International Business Machines Corporation Preventing hazard flushes in an instruction sequencing unit of a multi-slice processor
JP7032647B2 (en) * 2018-04-17 2022-03-09 富士通株式会社 Arithmetic processing unit and control method of arithmetic processing unit
US11386203B2 (en) * 2020-06-15 2022-07-12 Western Digital Technologies, Inc. Detection of compromised storage device firmware

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5293592A (en) * 1989-04-07 1994-03-08 Intel Corporatino Decoder for pipelined system having portion indicating type of address generation and other portion controlling address generation within pipeline
ES2138051T3 (en) * 1994-01-03 2000-01-01 Intel Corp METHOD AND APPARATUS FOR THE REALIZATION OF A SYSTEM OF RESOLUTION OF BIFURCATIONS IN FOUR STAGES IN A COMPUTER PROCESSOR.
US5649225A (en) 1994-06-01 1997-07-15 Advanced Micro Devices, Inc. Resynchronization of a superscalar processor
US5864707A (en) 1995-12-11 1999-01-26 Advanced Micro Devices, Inc. Superscalar microprocessor configured to predict return addresses from a return stack storage
US5740391A (en) 1996-03-01 1998-04-14 Hewlett-Packard Co. Preventing premature early exception signaling with special instruction encoding
US5822602A (en) * 1996-07-23 1998-10-13 S3 Incorporated Pipelined processor for executing repeated string instructions by halting dispatch after comparision to pipeline capacity
US6088793A (en) 1996-12-30 2000-07-11 Intel Corporation Method and apparatus for branch execution on a multiple-instruction-set-architecture microprocessor
US6026477A (en) 1997-12-31 2000-02-15 Intel Corporation Branch recovery mechanism to reduce processor front end stall time by providing path information for both correct and incorrect instructions mixed in the instruction pool
US6550002B1 (en) * 1999-11-04 2003-04-15 International Business Machines Corporation Method and system for detecting a flush of an instruction without a flush indicator
US6510508B1 (en) * 2000-06-15 2003-01-21 Advanced Micro Devices, Inc. Translation lookaside buffer flush filter

Also Published As

Publication number Publication date
SE0003446D0 (en) 2000-09-27
US6807621B2 (en) 2004-10-19
WO2002027480A1 (en) 2002-04-04
EP1323033A1 (en) 2003-07-02
US20020038417A1 (en) 2002-03-28
EP1323033B1 (en) 2015-09-16
SE0003446L (en) 2002-03-28

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