AU2001286835A1 - Syndrome assisted iterative decoder for turbo codes - Google Patents

Syndrome assisted iterative decoder for turbo codes

Info

Publication number
AU2001286835A1
AU2001286835A1 AU2001286835A AU8683501A AU2001286835A1 AU 2001286835 A1 AU2001286835 A1 AU 2001286835A1 AU 2001286835 A AU2001286835 A AU 2001286835A AU 8683501 A AU8683501 A AU 8683501A AU 2001286835 A1 AU2001286835 A1 AU 2001286835A1
Authority
AU
Australia
Prior art keywords
syndrome
turbo codes
iterative decoder
assisted iterative
assisted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001286835A
Inventor
Ofer Amrani
Meir Ariel
Reuven Meidan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of AU2001286835A1 publication Critical patent/AU2001286835A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6502—Reduction of hardware complexity or efficient processing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H03M13/2975—Judging correct decoding, e.g. iteration stopping criteria

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
AU2001286835A 2000-09-06 2001-08-28 Syndrome assisted iterative decoder for turbo codes Abandoned AU2001286835A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09655996 2000-09-06
US09/655,996 US6671852B1 (en) 2000-09-06 2000-09-06 Syndrome assisted iterative decoder for turbo codes
PCT/US2001/026758 WO2002021700A1 (en) 2000-09-06 2001-08-28 Syndrome assisted iterative decoder for turbo codes

Publications (1)

Publication Number Publication Date
AU2001286835A1 true AU2001286835A1 (en) 2002-03-22

Family

ID=24631221

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001286835A Abandoned AU2001286835A1 (en) 2000-09-06 2001-08-28 Syndrome assisted iterative decoder for turbo codes

Country Status (3)

Country Link
US (1) US6671852B1 (en)
AU (1) AU2001286835A1 (en)
WO (1) WO2002021700A1 (en)

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JP4389373B2 (en) * 2000-10-11 2009-12-24 ソニー株式会社 Decoder for iterative decoding of binary cyclic code
US7533320B2 (en) * 2000-11-14 2009-05-12 Interdigital Technology Corporation Wireless transmit/receive unit having a turbo decoder with circular redundancy code signature comparison and method
JP3540224B2 (en) * 2001-03-06 2004-07-07 シャープ株式会社 Turbo decoder, turbo decoding method, and storage medium storing the method
JP3512176B2 (en) * 2001-05-15 2004-03-29 松下電器産業株式会社 Turbo decoding device and method of controlling number of decoding repetitions in turbo decoding
US6826235B2 (en) * 2002-01-04 2004-11-30 Itran Communications Ltd. Robust communications system utilizing repetition code and cumulative decoder associated therewith
JP3889286B2 (en) * 2002-01-31 2007-03-07 三菱電機株式会社 Decoding method, decoding apparatus, and digital transmission system
JP3549519B2 (en) * 2002-04-26 2004-08-04 沖電気工業株式会社 Soft output decoder
US7266750B1 (en) 2002-07-10 2007-09-04 Maxtor Corporation Error recovery strategies for iterative decoders
JP4041445B2 (en) * 2003-09-19 2008-01-30 ソニー・エリクソン・モバイルコミュニケーションズ株式会社 Decoding device, communication device, and decoding method
EP1700380B1 (en) * 2003-12-23 2007-03-28 Telefonaktiebolaget LM Ericsson (publ) Turbo decoding with iterative estimation of channel parameters
US7490284B2 (en) * 2005-02-03 2009-02-10 Broadcom Corporation Meta-Viterbi algorithm for use in communication systems
US8171367B2 (en) * 2005-06-27 2012-05-01 Thomson Licensing Stopping criteria in iterative decoders
JP2008226300A (en) * 2007-03-09 2008-09-25 Nec Electronics Corp Method and circuit for decoding
US7904793B2 (en) * 2007-03-29 2011-03-08 Sandisk Corporation Method for decoding data in non-volatile storage using reliability metrics based on multiple reads
US7966546B2 (en) * 2007-03-31 2011-06-21 Sandisk Technologies Inc. Non-volatile memory with soft bit data transmission for error correction control
US7966550B2 (en) * 2007-03-31 2011-06-21 Sandisk Technologies Inc. Soft bit data transmission for error correction control in non-volatile memory
US7975209B2 (en) * 2007-03-31 2011-07-05 Sandisk Technologies Inc. Non-volatile memory with guided simulated annealing error correction control
US7971127B2 (en) * 2007-03-31 2011-06-28 Sandisk Technologies Inc. Guided simulated annealing in non-volatile memory error correction control
US8127216B2 (en) 2007-11-19 2012-02-28 Seagate Technology Llc Reduced state soft output processing
US20090132894A1 (en) * 2007-11-19 2009-05-21 Seagate Technology Llc Soft Output Bit Threshold Error Correction
US7978793B2 (en) * 2008-02-06 2011-07-12 Freescale Semiconductor, Inc. Method for generating soft decision signal from hard decision signal in a receiver system
US8296637B1 (en) 2008-09-22 2012-10-23 Marvell International Ltd. Channel quality monitoring and method for qualifying a storage channel using an iterative decoder
GB0915135D0 (en) * 2009-08-28 2009-10-07 Icera Inc Decoding signals received over a noisy channel
US8996967B2 (en) 2010-08-06 2015-03-31 Stmicroelectronics, Inc. Rendering data write errors detectable
US8745466B2 (en) * 2010-08-06 2014-06-03 Stmicroelectronics, Inc. Detecting data-write errors
EP2922209A1 (en) * 2014-03-20 2015-09-23 Technische Universität Kaiserslautern Soft decision decoding of linear block codes
US10454615B2 (en) * 2017-05-05 2019-10-22 Khalifa University of Science and Technology SD decoder for digital communications
US10304550B1 (en) 2017-11-29 2019-05-28 Sandisk Technologies Llc Sense amplifier with negative threshold sensing for non-volatile memory
US10643695B1 (en) 2019-01-10 2020-05-05 Sandisk Technologies Llc Concurrent multi-state program verify for non-volatile memory
US10979072B2 (en) * 2019-03-19 2021-04-13 Western Digital Technologies, Inc. Punctured bit estimation and bit error rate estimation
US11024392B1 (en) 2019-12-23 2021-06-01 Sandisk Technologies Llc Sense amplifier for bidirectional sensing of memory cells of a non-volatile memory

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Also Published As

Publication number Publication date
WO2002021700A1 (en) 2002-03-14
US6671852B1 (en) 2003-12-30

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