AU2001279252A1 - Method and apparatus for centralized snoop filtering - Google Patents

Method and apparatus for centralized snoop filtering

Info

Publication number
AU2001279252A1
AU2001279252A1 AU2001279252A AU7925201A AU2001279252A1 AU 2001279252 A1 AU2001279252 A1 AU 2001279252A1 AU 2001279252 A AU2001279252 A AU 2001279252A AU 7925201 A AU7925201 A AU 7925201A AU 2001279252 A1 AU2001279252 A1 AU 2001279252A1
Authority
AU
Australia
Prior art keywords
nodes
snoop
snoop filter
caches
switching device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001279252A
Inventor
Faye Briggs
Michel Cekleov
Kai Cheng
Manoj Khare
Lily Looi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2001279252A1 publication Critical patent/AU2001279252A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0822—Copy directories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0828—Cache consistency protocols using directory methods with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/507—Control mechanisms for virtual memory, cache or TLB using speculative control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Preparation Of Compounds By Using Micro-Organisms (AREA)

Abstract

An example embodiment of a computer system utilizing a central snoop filter includes several nodes coupled together via a switching device. Each of the nodes may include several processors and caches as well as a block of system memory. All traffic from one node to another takes place through the switching device. The switching device includes a snoop filter that tracks cache line coherency information for all caches in the computer system. The snoop filter has enough entries to track the tags and state information for all entries in all caches in all of the system's nodes. In addition to the tag and state information, the snoop filter stores information indicating which of the nodes has a copy of each cache line. The snoop filter serves in part to keep snoop transactions from being performed at nodes that do not contain a copy of the subject cache line, thereby reducing system overhead, reducing traffic across the system interconnect busses, and reducing the amount of time required to perform snoop transactions.
AU2001279252A 2000-08-21 2001-08-10 Method and apparatus for centralized snoop filtering Abandoned AU2001279252A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/643,382 2000-08-21
US09/643,382 US6810467B1 (en) 2000-08-21 2000-08-21 Method and apparatus for centralized snoop filtering
PCT/US2001/025061 WO2002017102A2 (en) 2000-08-21 2001-08-10 Method and apparatus for centralized snoop filtering

Publications (1)

Publication Number Publication Date
AU2001279252A1 true AU2001279252A1 (en) 2002-03-04

Family

ID=24580583

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001279252A Abandoned AU2001279252A1 (en) 2000-08-21 2001-08-10 Method and apparatus for centralized snoop filtering

Country Status (10)

Country Link
US (1) US6810467B1 (en)
EP (1) EP1311955B1 (en)
KR (1) KR100548908B1 (en)
CN (1) CN1329846C (en)
AT (1) ATE445187T1 (en)
AU (1) AU2001279252A1 (en)
DE (1) DE60140130D1 (en)
HK (1) HK1052773B (en)
TW (1) TW542964B (en)
WO (1) WO2002017102A2 (en)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE453152T1 (en) * 2001-05-01 2010-01-15 Sun Microsystems Inc SHARED MEMORY MULTIPROCESSOR SYSTEM USING MIXED BROADCAST SNOOP AND DIRECTORY BASED COHERENCE PROTOCOLS
US7222220B2 (en) * 2001-05-01 2007-05-22 Sun Microsystems, Inc. Multiprocessing system employing address switches to control mixed broadcast snooping and directory based coherency protocols transparent to active devices
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
US7093079B2 (en) * 2002-12-17 2006-08-15 Intel Corporation Snoop filter bypass
US7698509B1 (en) * 2004-07-13 2010-04-13 Oracle America, Inc. Snooping-based cache-coherence filter for a point-to-point connected multiprocessing node
US7213106B1 (en) * 2004-08-09 2007-05-01 Sun Microsystems, Inc. Conservative shadow cache support in a point-to-point connected multiprocessing node
US7469312B2 (en) * 2005-02-24 2008-12-23 International Business Machines Corporation Computer system bus bridge
US7275124B2 (en) * 2005-02-24 2007-09-25 International Business Machines Corporation Method and system for controlling forwarding or terminating of a request at a bus interface based on buffer availability
JP4956900B2 (en) * 2005-03-07 2012-06-20 富士通株式会社 Address snoop method and multiprocessor system
US7373462B2 (en) 2005-03-29 2008-05-13 International Business Machines Corporation Snoop filter for filtering snoop requests
US7380071B2 (en) * 2005-03-29 2008-05-27 International Business Machines Corporation Snoop filtering system in a multiprocessor system
US7392351B2 (en) * 2005-03-29 2008-06-24 International Business Machines Corporation Method and apparatus for filtering snoop requests using stream registers
US7797495B1 (en) * 2005-08-04 2010-09-14 Advanced Micro Devices, Inc. Distributed directory cache
US8099556B2 (en) * 2005-09-13 2012-01-17 Arm Limited Cache miss detection in a data processing apparatus
US8185724B2 (en) * 2006-03-03 2012-05-22 Arm Limited Monitoring values of signals within an integrated circuit
US20090031082A1 (en) * 2006-03-06 2009-01-29 Simon Andrew Ford Accessing a Cache in a Data Processing Apparatus
US7581068B2 (en) * 2006-06-29 2009-08-25 Intel Corporation Exclusive ownership snoop filter
US20080109624A1 (en) * 2006-11-03 2008-05-08 Gilbert Jeffrey D Multiprocessor system with private memory sections
US7937535B2 (en) * 2007-02-22 2011-05-03 Arm Limited Managing cache coherency in a data processing apparatus
US7996626B2 (en) * 2007-12-13 2011-08-09 Dell Products L.P. Snoop filter optimization
US8856456B2 (en) 2011-06-09 2014-10-07 Apple Inc. Systems, methods, and devices for cache block coherence
US9477600B2 (en) 2011-08-08 2016-10-25 Arm Limited Apparatus and method for shared cache control including cache lines selectively operable in inclusive or non-inclusive mode
US9058269B2 (en) * 2012-06-25 2015-06-16 Advanced Micro Devices, Inc. Method and apparatus including a probe filter for shared caches utilizing inclusion bits and a victim probe bit
US9122612B2 (en) * 2012-06-25 2015-09-01 Advanced Micro Devices, Inc. Eliminating fetch cancel for inclusive caches
CN105095254B (en) * 2014-05-07 2023-01-10 深圳市中兴微电子技术有限公司 Method and device for realizing data consistency
CN104239270A (en) * 2014-07-25 2014-12-24 浪潮(北京)电子信息产业有限公司 High-speed cache synchronization method and high-speed cache synchronization device
US9727466B2 (en) * 2014-08-26 2017-08-08 Arm Limited Interconnect and method of managing a snoop filter for an interconnect
US9639470B2 (en) * 2014-08-26 2017-05-02 Arm Limited Coherency checking of invalidate transactions caused by snoop filter eviction in an integrated circuit
US9507716B2 (en) * 2014-08-26 2016-11-29 Arm Limited Coherency checking of invalidate transactions caused by snoop filter eviction in an integrated circuit
US11237965B2 (en) * 2014-12-31 2022-02-01 Arteris, Inc. Configurable snoop filters for cache coherent systems
US10157133B2 (en) 2015-12-10 2018-12-18 Arm Limited Snoop filter for cache coherency in a data processing system
US9900260B2 (en) 2015-12-10 2018-02-20 Arm Limited Efficient support for variable width data channels in an interconnect network
US20170185516A1 (en) * 2015-12-28 2017-06-29 Arm Limited Snoop optimization for multi-ported nodes of a data processing system
US9990292B2 (en) * 2016-06-29 2018-06-05 Arm Limited Progressive fine to coarse grain snoop filter
US10346307B2 (en) 2016-09-28 2019-07-09 Samsung Electronics Co., Ltd. Power efficient snoop filter design for mobile platform
US10042766B1 (en) 2017-02-02 2018-08-07 Arm Limited Data processing apparatus with snoop request address alignment and snoop response time alignment
US11119926B2 (en) 2017-12-18 2021-09-14 Advanced Micro Devices, Inc. Region based directory scheme to adapt to large cache sizes
US10705959B2 (en) 2018-08-31 2020-07-07 Advanced Micro Devices, Inc. Region based split-directory scheme to adapt to large cache sizes
US10922237B2 (en) 2018-09-12 2021-02-16 Advanced Micro Devices, Inc. Accelerating accesses to private regions in a region-based cache directory scheme
US10769071B2 (en) * 2018-10-10 2020-09-08 Micron Technology, Inc. Coherent memory access
US10657055B1 (en) * 2018-12-13 2020-05-19 Arm Limited Apparatus and method for managing snoop operations
US11550720B2 (en) 2020-11-24 2023-01-10 Arm Limited Configurable cache coherency controller
CN112612726B (en) * 2020-12-08 2022-09-27 海光信息技术股份有限公司 Data storage method and device based on cache consistency, processing chip and server

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5950226A (en) 1996-07-01 1999-09-07 Sun Microsystems, Inc. Multiprocessing system employing a three-hop communication protocol
US6088769A (en) 1996-10-01 2000-07-11 International Business Machines Corporation Multiprocessor cache coherence directed by combined local and global tables
US6374330B1 (en) * 1997-04-14 2002-04-16 International Business Machines Corporation Cache-coherency protocol with upstream undefined state
US6338122B1 (en) * 1998-12-15 2002-01-08 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that speculatively forwards a read request to a remote processing node
US6374331B1 (en) 1998-12-30 2002-04-16 Hewlett-Packard Company Distributed directory cache coherence multi-processor computer architecture
US6651157B1 (en) 1999-10-15 2003-11-18 Silicon Graphics, Inc. Multi-processor system and method of accessing data therein

Also Published As

Publication number Publication date
EP1311955B1 (en) 2009-10-07
WO2002017102A2 (en) 2002-02-28
EP1311955A2 (en) 2003-05-21
CN1571958A (en) 2005-01-26
ATE445187T1 (en) 2009-10-15
KR100548908B1 (en) 2006-02-02
CN1329846C (en) 2007-08-01
WO2002017102A3 (en) 2003-01-23
DE60140130D1 (en) 2009-11-19
HK1052773A1 (en) 2003-09-26
TW542964B (en) 2003-07-21
KR20030025296A (en) 2003-03-28
HK1052773B (en) 2010-05-20
US6810467B1 (en) 2004-10-26

Similar Documents

Publication Publication Date Title
AU2001279252A1 (en) Method and apparatus for centralized snoop filtering
DE10394081B4 (en) Method and device for impressing write data into a cache memory
EP0301354A3 (en) Cache consistency protocol for multiprocessor system
CA2062910A1 (en) Optimum write-back strategy for directory-based cache coherence protocols
DE69223090D1 (en) Bus monitoring for computer system operators
TW351788B (en) Method and apparatus for caching system management mode information with other information
ES2196893T3 (en) DATA TREATMENT SYSTEM WITH NON-UNIFORM MEMORY ACCESS (NUMA) THAT SPECULATIVELY SENDS A READING REQUEST TO A REMOTE TREATMENT NODE.
DE69837377D1 (en) DATA TRANSMISSION SYSTEM AND METHOD
ATE197099T1 (en) SYSTEM AND PROCEDURES FOR BUSINESS PAYMENTS USING TRUST AGENTS
MX9706592A (en) Multi-processing cache coherency protocol on a local bus.
EP0750258A3 (en) Memory state recovering apparatus
MY124400A (en) System for determining whether a subsequent transaction may be allowed or must be allowed or must not be allowed to bypass a preceding transaction.
GB2360109A (en) Lender and insurer transaction processing system and method
EP0811930A3 (en) A ligning data transfer between two PCI1 bus
BR9814844A (en) "system and process to provide speculative arbitration for data transfer"
GB2357867A (en) Out-of-order snooping for multiprocessor computer systems
DE69616226D1 (en) Invalidation bus optimization for multiprocessors with directory-based coherence protocols
EP1380956A3 (en) System with a directory based coherency protocol and split ownership and access right coherence mechanism
EP0817088A3 (en) Flushing data buffers in a bridge between two PCI buses
DE59500117D1 (en) ARRANGEMENT WITH MASTER AND SLAVE UNITS
DE69621263D1 (en) Distributed data cache for multiprocessor system with cache
ATE363092T1 (en) SECURITY DEVICE AND METHOD FOR A DATA PROCESSING SYSTEM
EP0936553A3 (en) Cache coherency protocol with tagged state and historical information
SE9603271L (en) Connection data buffer
DE69636028D1 (en) Group management device for data units