AU2001273685A1 - Method for selecting an optimal level of redundancy in the design of memories - Google Patents

Method for selecting an optimal level of redundancy in the design of memories

Info

Publication number
AU2001273685A1
AU2001273685A1 AU2001273685A AU7368501A AU2001273685A1 AU 2001273685 A1 AU2001273685 A1 AU 2001273685A1 AU 2001273685 A AU2001273685 A AU 2001273685A AU 7368501 A AU7368501 A AU 7368501A AU 2001273685 A1 AU2001273685 A1 AU 2001273685A1
Authority
AU
Australia
Prior art keywords
redundancy
memories
selecting
design
optimal level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001273685A
Inventor
John Caywood
David Lepejian
Julie Segal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HEURISTICS PHYSICS LABORATORIES Inc
Original Assignee
HEURISTICS PHYSICS LAB Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HEURISTICS PHYSICS LAB Inc filed Critical HEURISTICS PHYSICS LAB Inc
Publication of AU2001273685A1 publication Critical patent/AU2001273685A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
AU2001273685A 2000-07-14 2001-07-11 Method for selecting an optimal level of redundancy in the design of memories Abandoned AU2001273685A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/616,806 US6745370B1 (en) 2000-07-14 2000-07-14 Method for selecting an optimal level of redundancy in the design of memories
US09616806 2000-07-14
PCT/US2001/041347 WO2002007167A2 (en) 2000-07-14 2001-07-11 Method for selecting an optimal level of redundancy in the design of memories

Publications (1)

Publication Number Publication Date
AU2001273685A1 true AU2001273685A1 (en) 2002-01-30

Family

ID=24471016

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001273685A Abandoned AU2001273685A1 (en) 2000-07-14 2001-07-11 Method for selecting an optimal level of redundancy in the design of memories

Country Status (3)

Country Link
US (1) US6745370B1 (en)
AU (1) AU2001273685A1 (en)
WO (1) WO2002007167A2 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7550800B2 (en) 2003-06-06 2009-06-23 Chih-Hsin Wang Method and apparatus transporting charges in semiconductor device and semiconductor memory device
US7613041B2 (en) * 2003-06-06 2009-11-03 Chih-Hsin Wang Methods for operating semiconductor device and semiconductor memory device
US7759719B2 (en) * 2004-07-01 2010-07-20 Chih-Hsin Wang Electrically alterable memory cell
US7297634B2 (en) * 2003-06-06 2007-11-20 Marvell World Trade Ltd. Method and apparatus for semiconductor device and semiconductor memory device
US7137085B1 (en) * 2004-06-01 2006-11-14 Advanced Micro Devices, Inc. Wafer level global bitmap characterization in integrated circuit technology development
FR2874440B1 (en) * 2004-08-17 2008-04-25 Oberthur Card Syst Sa METHOD AND DEVICE FOR PROCESSING DATA
US7411244B2 (en) * 2005-06-28 2008-08-12 Chih-Hsin Wang Low power electrically alterable nonvolatile memory cells and arrays
US20070006048A1 (en) * 2005-06-29 2007-01-04 Intel Corporation Method and apparatus for predicting memory failure in a memory system
US7506282B2 (en) * 2005-08-18 2009-03-17 International Business Machines Corporation Apparatus and methods for predicting and/or calibrating memory yields
US8072023B1 (en) 2007-11-12 2011-12-06 Marvell International Ltd. Isolation for non-volatile memory cell array
US8120088B1 (en) 2007-12-07 2012-02-21 Marvell International Ltd. Non-volatile memory cell and array
US7890900B2 (en) * 2008-08-19 2011-02-15 Synopsys, Inc. Various methods and apparatuses for effective yield enhancement of good chip dies having memories per wafer
US10789398B2 (en) * 2016-08-31 2020-09-29 Synopsys, Inc. Method and apparatus for SOC with optimal RSMA

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5269014A (en) * 1988-05-24 1993-12-07 Mitsubishi Denki Kabushiki Kaisha Automatic programming system with design review capabilities
US5475695A (en) * 1993-03-19 1995-12-12 Semiconductor Diagnosis & Test Corporation Automatic failure analysis system
US6185707B1 (en) * 1998-11-13 2001-02-06 Knights Technology, Inc. IC test software system for mapping logical functional test data of logic integrated circuits to physical representation

Also Published As

Publication number Publication date
US6745370B1 (en) 2004-06-01
WO2002007167A2 (en) 2002-01-24
WO2002007167A3 (en) 2002-06-27

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