AU2001270368A1 - Hierarchical design and test method and system, program product embodying the method and integrated circuit produced thereby - Google Patents
Hierarchical design and test method and system, program product embodying the method and integrated circuit produced therebyInfo
- Publication number
- AU2001270368A1 AU2001270368A1 AU2001270368A AU7036801A AU2001270368A1 AU 2001270368 A1 AU2001270368 A1 AU 2001270368A1 AU 2001270368 A AU2001270368 A AU 2001270368A AU 7036801 A AU7036801 A AU 7036801A AU 2001270368 A1 AU2001270368 A1 AU 2001270368A1
- Authority
- AU
- Australia
- Prior art keywords
- integrated circuit
- program product
- hierarchical design
- circuit produced
- product embodying
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318583—Design for test
- G01R31/318591—Tools
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318583—Design for test
- G01R31/318586—Design for test with partial scan or non-scannable parts
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/626,877 | 2000-07-27 | ||
US09/626,877 US6615392B1 (en) | 2000-07-27 | 2000-07-27 | Hierarchical design and test method and system, program product embodying the method and integrated circuit produced thereby |
PCT/CA2001/000882 WO2002010785A2 (en) | 2000-07-27 | 2001-06-15 | Hierarchical design and test method and system, program product embodying the method and integrated circuit produced thereby |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2001270368A1 true AU2001270368A1 (en) | 2002-02-13 |
Family
ID=24512231
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2001270368A Abandoned AU2001270368A1 (en) | 2000-07-27 | 2001-06-15 | Hierarchical design and test method and system, program product embodying the method and integrated circuit produced thereby |
Country Status (6)
Country | Link |
---|---|
US (1) | US6615392B1 (en) |
EP (1) | EP1303764A2 (en) |
JP (1) | JP2004518222A (en) |
AU (1) | AU2001270368A1 (en) |
CA (1) | CA2416655A1 (en) |
WO (1) | WO2002010785A2 (en) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7657810B2 (en) | 2006-02-03 | 2010-02-02 | Texas Instruments Incorporated | Scan testing using scan frames with embedded commands |
JP4083544B2 (en) * | 2002-11-18 | 2008-04-30 | 富士通株式会社 | Multi-cycle path analysis method |
US7739638B2 (en) * | 2003-03-06 | 2010-06-15 | Fujitsu Limited | Circuit analyzing device, circuit analyzing method, program, and computer readable information recording medium considering influence of signal input to peripheral circuit which does not have logical influence |
JP4563286B2 (en) * | 2005-03-08 | 2010-10-13 | パナソニック株式会社 | Automatic circuit generator |
US7512918B2 (en) * | 2005-08-17 | 2009-03-31 | Lsi Corporation | Multimode delay analysis for simplifying integrated circuit design timing models |
US7546568B2 (en) | 2005-12-19 | 2009-06-09 | Lsi Corporation | Automation of tie cell insertion, optimization and replacement by scan flip-flops to increase fault coverage |
KR100859833B1 (en) * | 2006-07-20 | 2008-09-23 | 주식회사 하이닉스반도체 | Semiconductor memory device |
US7448008B2 (en) * | 2006-08-29 | 2008-11-04 | International Business Machines Corporation | Method, system, and program product for automated verification of gating logic using formal verification |
JP4901702B2 (en) * | 2007-11-27 | 2012-03-21 | 株式会社東芝 | Circuit design method |
US8271918B2 (en) * | 2009-01-31 | 2012-09-18 | Mentor Graphics Corporation | Formal verification of clock domain crossings |
US8051347B2 (en) * | 2009-07-16 | 2011-11-01 | Texas Instruments Incorporated | Scan-enabled method and system for testing a system-on-chip |
US8381144B2 (en) * | 2010-03-03 | 2013-02-19 | Qualcomm Incorporated | System and method of test mode gate operation |
US8566658B2 (en) * | 2011-03-25 | 2013-10-22 | Lsi Corporation | Low-power and area-efficient scan cell for integrated circuit testing |
KR101457557B1 (en) | 2013-01-18 | 2014-11-04 | 연세대학교 산학협력단 | Multi-core device, test device and method for diagnosing failure |
DE102014103703A1 (en) * | 2014-03-18 | 2015-09-24 | Airbus Defence and Space GmbH | Verification and certification of an electronic component |
TWI739716B (en) * | 2021-03-03 | 2021-09-11 | 瑞昱半導體股份有限公司 | Test circuit |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0746120B2 (en) | 1986-03-10 | 1995-05-17 | 株式会社東芝 | Test facilitation circuit and test method |
US5067091A (en) | 1988-01-21 | 1991-11-19 | Kabushiki Kaisha Toshiba | Circuit design conversion apparatus |
EP0419734B1 (en) | 1989-08-25 | 1995-06-14 | Koninklijke Philips Electronics N.V. | Method for testing a hierarchically organised integrated circuit device, and integrated circuit device suitable for being so tested |
US5323400A (en) * | 1991-09-09 | 1994-06-21 | Northern Telecom Limited | Scan cell for weighted random pattern generation and method for its operation |
GR920100088A (en) * | 1992-03-05 | 1993-11-30 | Consulting R & D Corp Koloni S | Transparent testing of integrated circuits. |
US5903578A (en) | 1996-03-08 | 1999-05-11 | Lsi Logic Corporation | Test shells for protecting proprietary information in asic cores |
US5638380A (en) | 1996-03-14 | 1997-06-10 | Lsi Logic Corp. | Protecting proprietary asic design information using boundary scan on selective inputs and outputs |
US5696771A (en) | 1996-05-17 | 1997-12-09 | Synopsys, Inc. | Method and apparatus for performing partial unscan and near full scan within design for test applications |
US6067409A (en) * | 1996-06-28 | 2000-05-23 | Lsi Logic Corporation | Advanced modular cell placement system |
US5828579A (en) | 1996-08-28 | 1998-10-27 | Synopsys, Inc. | Scan segment processing within hierarchical scan architecture for design for test applications |
US5949692A (en) | 1996-08-28 | 1999-09-07 | Synopsys, Inc. | Hierarchical scan architecture for design for test applications |
US6378093B1 (en) * | 1998-02-10 | 2002-04-23 | Texas Instruments Incorporated | Controller for scan distributor and controller architecture |
US6405335B1 (en) * | 1998-02-25 | 2002-06-11 | Texas Instruments Incorporated | Position independent testing of circuits |
US6405355B1 (en) * | 1999-03-24 | 2002-06-11 | Synopsys, Inc. | Method for placement-based scan-in and scan-out ports selection |
-
2000
- 2000-07-27 US US09/626,877 patent/US6615392B1/en not_active Expired - Lifetime
-
2001
- 2001-06-15 EP EP01949122A patent/EP1303764A2/en not_active Withdrawn
- 2001-06-15 AU AU2001270368A patent/AU2001270368A1/en not_active Abandoned
- 2001-06-15 WO PCT/CA2001/000882 patent/WO2002010785A2/en not_active Application Discontinuation
- 2001-06-15 JP JP2002561246A patent/JP2004518222A/en active Pending
- 2001-06-15 CA CA002416655A patent/CA2416655A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
WO2002010785A2 (en) | 2002-02-07 |
US6615392B1 (en) | 2003-09-02 |
EP1303764A2 (en) | 2003-04-23 |
WO2002010785A3 (en) | 2002-12-27 |
JP2004518222A (en) | 2004-06-17 |
CA2416655A1 (en) | 2002-02-07 |
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