AU2001266826A1 - Partitioned content addressable memory device - Google Patents

Partitioned content addressable memory device

Info

Publication number
AU2001266826A1
AU2001266826A1 AU2001266826A AU6682601A AU2001266826A1 AU 2001266826 A1 AU2001266826 A1 AU 2001266826A1 AU 2001266826 A AU2001266826 A AU 2001266826A AU 6682601 A AU6682601 A AU 6682601A AU 2001266826 A1 AU2001266826 A1 AU 2001266826A1
Authority
AU
Australia
Prior art keywords
cam
cam blocks
blocks
block
block select
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001266826A
Inventor
Jose Pio Pereira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Netlogic I LLC
Original Assignee
Netlogic Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/590,428 external-priority patent/US6763425B1/en
Priority claimed from US09/590,642 external-priority patent/US6324087B1/en
Priority claimed from US09/590,775 external-priority patent/US6687785B1/en
Application filed by Netlogic Microsystems Inc filed Critical Netlogic Microsystems Inc
Publication of AU2001266826A1 publication Critical patent/AU2001266826A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F16/00—Information retrieval; Database structures therefor; File system structures therefor
    • G06F16/90—Details of database functions independent of the retrieved data types
    • G06F16/903—Querying
    • G06F16/90335—Query processing
    • G06F16/90339—Query processing by using parallel associative memories or content-addressable memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores

Abstract

A CAM device having a plurality of CAM blocks is partitioned into a number of individually searchable partitions, where each partition may include one or more CAM blocks of the CAM device. In one embodiment, each CAM block is connected to a block select circuit that stores a class code indicating what class or type of data is stored in the block. The same class code may be stored in any number of block select circuits to define a partition as including the corresponding number of CAM blocks. During compare operations between a comparand word and data stored in the CAM device, a search code provided to the block select circuits is compared to the class codes to selectively enable or disable the CAM blocks for the compare operation. In some embodiments, the block select circuits may be used to disable defective CAM blocks. In such embodiments, address translation logic is used to translate addresses in defective CAM blocks to addresses in non-defective CAM blocks, and a main priority encoder is used to dynamically assign priority between the CAM blocks.
AU2001266826A 2000-06-08 2001-06-08 Partitioned content addressable memory device Abandoned AU2001266826A1 (en)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US09/590,428 2000-06-08
US09/590,642 2000-06-08
US09/590,775 2000-06-08
US09/590,428 US6763425B1 (en) 2000-06-08 2000-06-08 Method and apparatus for address translation in a partitioned content addressable memory device
US09/590,642 US6324087B1 (en) 2000-06-08 2000-06-08 Method and apparatus for partitioning a content addressable memory device
US09/590,775 US6687785B1 (en) 2000-06-08 2000-06-08 Method and apparatus for re-assigning priority in a partitioned content addressable memory device
PCT/US2001/018736 WO2001095336A2 (en) 2000-06-08 2001-06-08 Partitioned content addressable memory device

Publications (1)

Publication Number Publication Date
AU2001266826A1 true AU2001266826A1 (en) 2001-12-17

Family

ID=27416568

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001266826A Abandoned AU2001266826A1 (en) 2000-06-08 2001-06-08 Partitioned content addressable memory device

Country Status (6)

Country Link
EP (1) EP1290697B1 (en)
JP (1) JP2003536197A (en)
AT (1) ATE493733T1 (en)
AU (1) AU2001266826A1 (en)
DE (1) DE60143745D1 (en)
WO (1) WO2001095336A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6542391B2 (en) * 2000-06-08 2003-04-01 Netlogic Microsystems, Inc. Content addressable memory with configurable class-based storage partition
JP2003303495A (en) * 2002-04-09 2003-10-24 Fujitsu Ltd Semiconductor memory device
US6925464B2 (en) * 2002-06-13 2005-08-02 Intel Corporation Method and system for performing inserts and lookups in memory
JP5245169B2 (en) * 2008-06-19 2013-07-24 マーベル ワールド トレード リミテッド Integrated chip, semiconductor chip, and method

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06251589A (en) * 1993-03-02 1994-09-09 Hitachi Ltd Associative memory input/output control circuit
JPH0721785A (en) * 1993-06-29 1995-01-24 Kawasaki Steel Corp Semiconductor memory
US5602795A (en) * 1994-01-12 1997-02-11 Sun Microsystems, Inc. Method and apparatus for implementing a high-speed dynamic line driver
JP3703518B2 (en) * 1995-03-30 2005-10-05 川崎マイクロエレクトロニクス株式会社 Associative memory system
US5818350A (en) * 1995-04-11 1998-10-06 Lexar Microsystems Inc. High performance method of and system for selecting one of a plurality of IC chip while requiring minimal select lines
US6041389A (en) * 1995-11-16 2000-03-21 E Cirrus Logic, Inc. Memory architecture using content addressable memory, and systems and methods using the same
JP3816560B2 (en) * 1995-12-25 2006-08-30 株式会社ルネサステクノロジ Associative memory circuit test method and associative memory circuit test circuit
JP3190868B2 (en) * 1997-11-21 2001-07-23 エヌイーシーマイクロシステム株式会社 Associative memory device
US6044005A (en) * 1999-02-03 2000-03-28 Sibercore Technologies Incorporated Content addressable memory storage device

Also Published As

Publication number Publication date
ATE493733T1 (en) 2011-01-15
EP1290697A2 (en) 2003-03-12
WO2001095336A2 (en) 2001-12-13
JP2003536197A (en) 2003-12-02
EP1290697B1 (en) 2010-12-29
DE60143745D1 (en) 2011-02-10
WO2001095336A3 (en) 2002-07-25

Similar Documents

Publication Publication Date Title
US6246601B1 (en) Method and apparatus for using an inter-row configurable content addressable memory
US6910097B1 (en) Classless interdomain routing using binary content addressable memory
US7831765B2 (en) Distributed programmable priority encoder capable of finding the longest match in a single operation
US6502163B1 (en) Method and apparatus for ordering entries in a ternary content addressable memory
US6252789B1 (en) Inter-row configurability of content addressable memory
US6243281B1 (en) Method and apparatus for accessing a segment of CAM cells in an intra-row configurable CAM system
KR970071283A (en) Cache Memory and How It Works
US6275406B1 (en) Content address memory circuit with redundant array and method for implementing the same
US4831522A (en) Circuit and method for page addressing read only memory
US20070038906A1 (en) Column/row redundancy architecture using latches programmed from a look up table
US6374325B1 (en) Content addressable memory (CAM)
BR0108811A (en) Simultaneous multiple bank operation for a flash memory
JPS635839B2 (en)
ATE362179T1 (en) CIRCUIT AND METHOD FOR PERFORMING VARIABLE-WIDTH SEARCH OPERATIONS IN A CONTENT-ADDRESSABLE MEMORY
KR960018907A (en) Apparatus and Method for Efficiently Sharing Virtual Storage Conversions
GB1532278A (en) Data processing system and memory module therefor
US6718432B1 (en) Method and apparatus for transparent cascading of multiple content addressable memory devices
US6169685B1 (en) Content addressable memories
AU2001266826A1 (en) Partitioned content addressable memory device
US6751701B1 (en) Method and apparatus for detecting a multiple match in an intra-row configurable CAM system
US6799243B1 (en) Method and apparatus for detecting a match in an intra-row configurable cam system
US6937491B2 (en) Multi-bank content addressable memory (CAM) devices having segment-based priority resolution circuits therein and methods operating same
US6813680B1 (en) Method and apparatus for loading comparand data into a content addressable memory system
US6801981B1 (en) Intra-row configurability of content addressable memory
US4497020A (en) Selective mapping system and method