AU2001266700A1 - Power saving scheme for burst mode implementation during reading of data from a memory device - Google Patents
Power saving scheme for burst mode implementation during reading of data from a memory deviceInfo
- Publication number
- AU2001266700A1 AU2001266700A1 AU2001266700A AU6670001A AU2001266700A1 AU 2001266700 A1 AU2001266700 A1 AU 2001266700A1 AU 2001266700 A AU2001266700 A AU 2001266700A AU 6670001 A AU6670001 A AU 6670001A AU 2001266700 A1 AU2001266700 A1 AU 2001266700A1
- Authority
- AU
- Australia
- Prior art keywords
- data
- memory device
- power saving
- burst mode
- during reading
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1069—I/O lines read out arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
- G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US21013400P | 2000-06-07 | 2000-06-07 | |
| US60210134 | 2000-06-07 | ||
| US09729388 | 2000-12-04 | ||
| US09/729,388 US6463003B2 (en) | 2000-06-07 | 2000-12-04 | Power saving scheme for burst mode implementation during reading of data from a memory device |
| PCT/US2001/018080 WO2001095334A2 (en) | 2000-06-07 | 2001-06-04 | Power saving scheme for burst mode implementation during reading of data from a memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| AU2001266700A1 true AU2001266700A1 (en) | 2001-12-17 |
Family
ID=26904850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AU2001266700A Abandoned AU2001266700A1 (en) | 2000-06-07 | 2001-06-04 | Power saving scheme for burst mode implementation during reading of data from a memory device |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6463003B2 (en) |
| AU (1) | AU2001266700A1 (en) |
| TW (1) | TW594464B (en) |
| WO (1) | WO2001095334A2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI417719B (en) * | 2007-08-09 | 2013-12-01 | Ibm | Method, apparatus and computer program product providing instruction monitoring for reduction of energy usage and energy reduction when storing data in a memory |
| JP5738639B2 (en) * | 2011-03-24 | 2015-06-24 | オリンパス株式会社 | Data processing apparatus and data processing method |
| JP5972549B2 (en) * | 2011-09-29 | 2016-08-17 | ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． | Semiconductor device |
| JP6219631B2 (en) * | 2013-07-29 | 2017-10-25 | 学校法人明星学苑 | Logic unit |
| US10210923B2 (en) * | 2017-07-12 | 2019-02-19 | International Business Machines Corporation | Activation of memory core circuits in an integrated circuit |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07111835B2 (en) * | 1983-08-24 | 1995-11-29 | 株式会社日立製作所 | Semiconductor device |
| KR0172366B1 (en) | 1995-11-10 | 1999-03-30 | 김광호 | Non-volatile semiconductor memory device |
| KR100272171B1 (en) | 1998-08-19 | 2000-12-01 | 윤종용 | Data input/output system reducing power consumption and input/output method using the same |
| US6292425B1 (en) * | 2000-06-07 | 2001-09-18 | Advanced Micro Devices, Inc. | Power saving on the fly during reading of data from a memory device |
-
2000
- 2000-12-04 US US09/729,388 patent/US6463003B2/en not_active Expired - Lifetime
-
2001
- 2001-06-04 AU AU2001266700A patent/AU2001266700A1/en not_active Abandoned
- 2001-06-04 WO PCT/US2001/018080 patent/WO2001095334A2/en active Application Filing
- 2001-06-06 TW TW090113660A patent/TW594464B/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| WO2001095334A3 (en) | 2002-06-06 |
| WO2001095334A2 (en) | 2001-12-13 |
| US6463003B2 (en) | 2002-10-08 |
| TW594464B (en) | 2004-06-21 |
| US20010050874A1 (en) | 2001-12-13 |
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