AU2001265156A1 - Systems and methods for generating hardware description code - Google Patents

Systems and methods for generating hardware description code

Info

Publication number
AU2001265156A1
AU2001265156A1 AU2001265156A AU6515601A AU2001265156A1 AU 2001265156 A1 AU2001265156 A1 AU 2001265156A1 AU 2001265156 A AU2001265156 A AU 2001265156A AU 6515601 A AU6515601 A AU 6515601A AU 2001265156 A1 AU2001265156 A1 AU 2001265156A1
Authority
AU
Australia
Prior art keywords
systems
methods
hardware description
description code
generating hardware
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001265156A
Inventor
Alvin Swee Hock Lim
Spencer Hao Tiong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of AU2001265156A1 publication Critical patent/AU2001265156A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G01R31/318357—Simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318364—Generation of test inputs, e.g. test vectors, patterns or sequences as a result of hardware simulation, e.g. in an HDL environment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318583—Design for test
    • G01R31/318591—Tools
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/02—CAD in a network environment, e.g. collaborative CAD or distributed simulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/99941—Database schema or data structure
    • Y10S707/99942—Manipulating data structure, e.g. compression, compaction, compilation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/99941—Database schema or data structure
    • Y10S707/99943—Generating database or data structure, e.g. via user interface
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/99941—Database schema or data structure
    • Y10S707/99944—Object-oriented database structure
    • Y10S707/99945—Object-oriented database structure processing
AU2001265156A 2000-11-28 2001-05-29 Systems and methods for generating hardware description code Abandoned AU2001265156A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/724,134 2000-11-28
US09/724,134 US6539520B1 (en) 2000-11-28 2000-11-28 Systems and methods for generating hardware description code
PCT/US2001/017397 WO2002043463A2 (en) 2000-11-28 2001-05-29 Systems and methods for generating hardware description code

Publications (1)

Publication Number Publication Date
AU2001265156A1 true AU2001265156A1 (en) 2002-06-11

Family

ID=24909155

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001265156A Abandoned AU2001265156A1 (en) 2000-11-28 2001-05-29 Systems and methods for generating hardware description code

Country Status (8)

Country Link
US (1) US6539520B1 (en)
EP (1) EP1364318A2 (en)
JP (1) JP2004514995A (en)
KR (1) KR20030066684A (en)
CN (1) CN1484799A (en)
AU (1) AU2001265156A1 (en)
TW (1) TW552555B (en)
WO (1) WO2002043463A2 (en)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7051015B1 (en) * 2000-01-10 2006-05-23 Wind River Systems, Inc. System and method for implementing a flexible data-driven target object model
US7206730B2 (en) * 2001-04-11 2007-04-17 Oleandr Pochayevets HDL preprocessor
US7464016B2 (en) * 2001-11-09 2008-12-09 Sun Microsystems, Inc. Hot plug and hot pull system simulation
US6721923B2 (en) * 2002-02-20 2004-04-13 Agilent Technologies, Inc. System and method for generating integrated circuit boundary register description data
US20040010766A1 (en) * 2002-07-10 2004-01-15 Swope John M. Method and system for automated design of printed circuit boards
US6973631B2 (en) * 2002-07-18 2005-12-06 Incentia Design Systems Corp. Scan insertion with bypass login in an IC design
JP4426166B2 (en) * 2002-11-01 2010-03-03 ユー・エム・シー・ジャパン株式会社 Semiconductor device design method, semiconductor device design program, and semiconductor device
US7086047B1 (en) * 2002-12-04 2006-08-01 Xilinx, Inc. Determining hardware generated by high level language compilation through loop optimizations
EP1426885B1 (en) * 2002-12-04 2017-01-04 Mentor Graphics Corporation Generation of a multiplicity of parameterised HDLs
US7152123B2 (en) * 2002-12-23 2006-12-19 Micron Technology, Inc. Distributed configuration storage
US7137087B1 (en) * 2003-08-20 2006-11-14 Adaptec, Inc. Integrated circuit verification scheme
CN1306398C (en) * 2003-09-11 2007-03-21 华为技术有限公司 Method for acquiring file status by using Verilog hardware description language
US7222313B2 (en) * 2003-10-09 2007-05-22 Finisar Corporation Creating description files used to configure components in a distributed system
US20050097416A1 (en) * 2003-10-31 2005-05-05 Dominic Plunkett Testing of integrated circuits using boundary scan
US20050102488A1 (en) * 2003-11-07 2005-05-12 Bullis George A. Firmware description language for accessing firmware registers
US7536377B1 (en) 2003-12-18 2009-05-19 Xilinx, Inc. Component naming
US7770147B1 (en) * 2004-03-08 2010-08-03 Adaptec, Inc. Automatic generators for verilog programming
US7404156B2 (en) * 2004-06-03 2008-07-22 Lsi Corporation Language and templates for use in the design of semiconductor products
US7398492B2 (en) * 2004-06-03 2008-07-08 Lsi Corporation Rules and directives for validating correct data used in the design of semiconductor products
US20060075392A1 (en) * 2004-10-05 2006-04-06 International Business Machines Corporation System and method for reverse engineering of pattern string validation scripts
US8402449B1 (en) * 2008-01-10 2013-03-19 The Mathworks, Inc. Technique for automatically assigning placement for pipeline registers within code generated from a program specification
GR1006530B (en) * 2008-05-28 2009-09-10 Ερευνα Και Τεχνολογια Θινκ Σιλικον Ε.Π.Ε.-Think Silicon Ltd. Method for twe automated receiving of parameters of sub-systems of micro-electronic circuits for use in integrated circuits.
KR20110081961A (en) * 2008-09-30 2011-07-15 가부시키가이샤 어드밴티스트 Circuit design method, circuit design system, and recording medium
US20100175038A1 (en) * 2009-01-06 2010-07-08 Internationl Buisness Machines Corporation Techniques for Implementing an Engineering Change Order in an Integrated Circuit Design
US20100275146A1 (en) * 2009-04-24 2010-10-28 Dell Products, Lp System and method for managing devices in an information handling system
US20100281429A1 (en) * 2009-04-30 2010-11-04 Bigmachines, Inc. Methods and apparatus for configuring a product using an array of configuration sets
US8146027B1 (en) * 2009-05-07 2012-03-27 Xilinx, Inc. Creating interfaces for importation of modules into a circuit design
US8156457B2 (en) * 2009-09-24 2012-04-10 Synopsys, Inc. Concurrent simulation of hardware designs with behavioral characteristics
US8856701B1 (en) * 2013-03-12 2014-10-07 Taiwan Semiconductor Manufacturing Co., Ltd. Method of radio-frequency and microwave device generation
CN113496105A (en) * 2020-03-20 2021-10-12 洛极豪斯私人有限公司 Method for synthesizing RTL description of HDL for digital circuit design

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5682392A (en) * 1994-09-28 1997-10-28 Teradyne, Inc. Method and apparatus for the automatic generation of boundary scan description language files
US6023565A (en) * 1996-03-29 2000-02-08 Xilinx, Inc. Method for configuring circuits over a data communications link
GB2321322B (en) * 1996-10-28 2001-10-10 Altera Corp Remote software technical support
US5815683A (en) * 1996-11-05 1998-09-29 Mentor Graphics Corporation Accessing a remote cad tool server
US5966707A (en) * 1997-12-02 1999-10-12 International Business Machines Corporation Method for managing a plurality of data processes residing in heterogeneous data repositories
JPH11224284A (en) * 1998-02-09 1999-08-17 Fujitsu Ltd Distribution system and device for semiconductor design resources and medium for storing software for distribution device
US6421818B1 (en) * 1998-02-20 2002-07-16 Lsi Logic Corporation Efficient top-down characterization method
US6292925B1 (en) * 1998-03-27 2001-09-18 Xilinx, Inc. Context-sensitive self implementing modules
US6226780B1 (en) * 1998-08-31 2001-05-01 Mentor Graphics Corporation Circuit design method and apparatus supporting a plurality of hardware design languages
US6289489B1 (en) * 1999-02-23 2001-09-11 Stephen L. Bold Method and apparatus for automatically cross-referencing graphical objects and HDL statements
US6366874B1 (en) * 1999-05-24 2002-04-02 Novas Software, Inc. System and method for browsing graphically an electronic design based on a hardware description language specification

Also Published As

Publication number Publication date
WO2002043463A3 (en) 2003-07-24
EP1364318A2 (en) 2003-11-26
JP2004514995A (en) 2004-05-20
CN1484799A (en) 2004-03-24
WO2002043463A2 (en) 2002-06-06
TW552555B (en) 2003-09-11
KR20030066684A (en) 2003-08-09
US6539520B1 (en) 2003-03-25

Similar Documents

Publication Publication Date Title
AU2001265156A1 (en) Systems and methods for generating hardware description code
AU2001259108A1 (en) Methods and systems for generating source code for object-oriented elements
AU2001239976A1 (en) System and method for common code generation
AU2001234771A1 (en) Combinatorial query generating system and method
AU2002214227A1 (en) Speech generating system and method
AU2002238019A1 (en) System and method for generating and maintaining software code
AU2001286956A1 (en) Software development systems and methods
AU2001298063A1 (en) Methods and systems for generating business models
AU2001258701A1 (en) Systems and methods for presenting and/or converting messages
AU2001257572A1 (en) Method and system for account activation
AU2002239612A1 (en) Systems and methods for positioning teeth
AU2001261225A1 (en) Method and system for hardware simulation
AU2002245226A1 (en) Systems and methods for coding competitions
AU2001245811A1 (en) Database system and method
AU2001255205A1 (en) Systems and methods for generating computer-displayed presentations
AU2001244302A1 (en) Assessment methods and systems
AU2001253733A1 (en) Video-monitoring safety systems and methods
AU2002213227A1 (en) Generalizer system and method
AUPQ555400A0 (en) Laser system and methods
AU2001253314A1 (en) Positioning systems and related methods
AU2001255677A1 (en) Systems and methods for generating an appliance with tie points
AUPR890201A0 (en) Methods and systems (npw005)
AU1803401A (en) Methods and systems for generating tractograms
AU2001275352A1 (en) Anti-pilferage system
AU2002215390A1 (en) Audit system and method