AU2001264026A1 - Method for cryptographic calculation comprising a modular exponentiation routine - Google Patents

Method for cryptographic calculation comprising a modular exponentiation routine

Info

Publication number
AU2001264026A1
AU2001264026A1 AU2001264026A AU6402601A AU2001264026A1 AU 2001264026 A1 AU2001264026 A1 AU 2001264026A1 AU 2001264026 A AU2001264026 A AU 2001264026A AU 6402601 A AU6402601 A AU 6402601A AU 2001264026 A1 AU2001264026 A1 AU 2001264026A1
Authority
AU
Australia
Prior art keywords
cryptographic calculation
modular exponentiation
routine
exponentiation routine
modular
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001264026A
Inventor
David Naccache
Christophe Tymen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gemplus SA
Original Assignee
Gemplus Card International SA
Gemplus SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gemplus Card International SA, Gemplus SA filed Critical Gemplus Card International SA
Publication of AU2001264026A1 publication Critical patent/AU2001264026A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/723—Modular exponentiation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219—Countermeasures against side channel or fault attacks
    • G06F2207/7223—Randomisation as countermeasure against side channel attacks
    • G06F2207/7233—Masking, e.g. (A**e)+r mod n
    • G06F2207/7238—Operand masking, i.e. message blinding, e.g. (A+r)**e mod n; k.(P+R)

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Security & Cryptography (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Storage Device Security (AREA)
AU2001264026A 2000-06-13 2001-05-25 Method for cryptographic calculation comprising a modular exponentiation routine Abandoned AU2001264026A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0007528A FR2810178B1 (en) 2000-06-13 2000-06-13 CRYPTOGRAPHIC CALCULATION PROCESS INCLUDING A MODULAR EXPONENTIATION ROUTINE
FR0007528 2000-06-13
PCT/FR2001/001622 WO2001097009A1 (en) 2000-06-13 2001-05-25 Method for cryptographic calculation comprising a modular exponentiation routine

Publications (1)

Publication Number Publication Date
AU2001264026A1 true AU2001264026A1 (en) 2001-12-24

Family

ID=8851219

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001264026A Abandoned AU2001264026A1 (en) 2000-06-13 2001-05-25 Method for cryptographic calculation comprising a modular exponentiation routine

Country Status (3)

Country Link
AU (1) AU2001264026A1 (en)
FR (1) FR2810178B1 (en)
WO (1) WO2001097009A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2867335A1 (en) * 2004-03-02 2005-09-09 France Telecom Cryptographic method for e.g. authenticating integrated circuit chip, involves multiplying secret key by number using predecomposition of key as product of whole numbers whose binary decomposition has hamming weight lower than that of key
FR2880148A1 (en) * 2004-12-23 2006-06-30 Gemplus Sa SECURE AND COMPACT EXPONENTIATION METHOD FOR CRYPTOGRAPHY
EP1899804B1 (en) * 2005-06-29 2012-11-07 Irdeto B.V. Arrangement for and method of protecting a data processing device against a cryptographic attack or analysis
DE102005032731A1 (en) * 2005-07-13 2007-01-25 Siemens Ag Method for side channel resistant multiplication
US9959429B2 (en) 2013-03-15 2018-05-01 Cryptography Research, Inc. Asymmetrically masked multiplication

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5991415A (en) * 1997-05-12 1999-11-23 Yeda Research And Development Co. Ltd. At The Weizmann Institute Of Science Method and apparatus for protecting public key schemes from timing and fault attacks

Also Published As

Publication number Publication date
FR2810178A1 (en) 2001-12-14
FR2810178B1 (en) 2004-10-29
WO2001097009A1 (en) 2001-12-20

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