AU2001263176A1 - Redundancy analysis method and apparatus for memory testing - Google Patents

Redundancy analysis method and apparatus for memory testing

Info

Publication number
AU2001263176A1
AU2001263176A1 AU2001263176A AU6317601A AU2001263176A1 AU 2001263176 A1 AU2001263176 A1 AU 2001263176A1 AU 2001263176 A AU2001263176 A AU 2001263176A AU 6317601 A AU6317601 A AU 6317601A AU 2001263176 A1 AU2001263176 A1 AU 2001263176A1
Authority
AU
Australia
Prior art keywords
analysis method
memory testing
redundancy analysis
redundancy
testing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001263176A
Inventor
Sung Hong
Steven A. Michaelson
Daniel Olster
Arthur Yaffe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Teradyne Inc
Original Assignee
Teradyne Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teradyne Inc filed Critical Teradyne Inc
Publication of AU2001263176A1 publication Critical patent/AU2001263176A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/72—Masking faults in memories by using spares or by reconfiguring with optimized replacement algorithms
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
AU2001263176A 2000-05-17 2001-05-16 Redundancy analysis method and apparatus for memory testing Abandoned AU2001263176A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09574689 2000-05-17
US09/574,689 US6499118B1 (en) 2000-05-17 2000-05-17 Redundancy analysis method and apparatus for ATE
PCT/US2001/015783 WO2001093276A1 (en) 2000-05-17 2001-05-16 Redundancy analysis method and apparatus for memory testing

Publications (1)

Publication Number Publication Date
AU2001263176A1 true AU2001263176A1 (en) 2001-12-11

Family

ID=24297200

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001263176A Abandoned AU2001263176A1 (en) 2000-05-17 2001-05-16 Redundancy analysis method and apparatus for memory testing

Country Status (6)

Country Link
US (1) US6499118B1 (en)
KR (1) KR100795520B1 (en)
AU (1) AU2001263176A1 (en)
MY (1) MY121478A (en)
TW (1) TW497193B (en)
WO (1) WO2001093276A1 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1273923A1 (en) * 2001-07-03 2003-01-08 Koninklijke Philips Electronics N.V. Testing a batch of electrical components
US7253650B2 (en) * 2004-05-25 2007-08-07 International Business Machines Corporation Increase productivity at wafer test using probe retest data analysis
US7423442B2 (en) * 2005-07-22 2008-09-09 Texas Instruments Incorporated System and method for early qualification of semiconductor devices
US20080270854A1 (en) 2007-04-24 2008-10-30 Micron Technology, Inc. System and method for running test and redundancy analysis in parallel
US11360840B2 (en) 2020-01-20 2022-06-14 Samsung Electronics Co., Ltd. Method and apparatus for performing redundancy analysis of a semiconductor device
US11456049B2 (en) * 2020-07-02 2022-09-27 Micron Technology, Inc. Memory device testing, and associated methods, devices, and systems
US11797371B2 (en) 2020-08-18 2023-10-24 Changxin Memory Technologies, Inc. Method and device for determining fail bit repair scheme
EP3985675B1 (en) 2020-08-18 2024-01-31 Changxin Memory Technologies, Inc. Method and device for repairing fail bits
US11887685B2 (en) 2020-08-18 2024-01-30 Changxin Memory Technologies, Inc. Fail Bit repair method and device
US11791010B2 (en) 2020-08-18 2023-10-17 Changxin Memory Technologies, Inc. Method and device for fail bit repairing
US20220310187A1 (en) * 2021-03-26 2022-09-29 Changxin Memory Technologies, Inc. Redundant circuit assigning method and device, and medium
US11791012B2 (en) 2021-03-31 2023-10-17 Changxin Memory Technologies, Inc. Standby circuit dispatch method, apparatus, device and medium
US11881278B2 (en) * 2021-03-31 2024-01-23 Changxin Memory Technologies, Inc. Redundant circuit assigning method and device, apparatus and medium

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0670668B2 (en) * 1989-09-08 1994-09-07 株式会社東芝 Electronic component inspection device
US5588115A (en) * 1993-01-29 1996-12-24 Teradyne, Inc. Redundancy analyzer for automatic memory tester
US5522038A (en) * 1993-04-16 1996-05-28 Micron Technology, Inc. Testing mapped signal sources
US5795797A (en) * 1995-08-18 1998-08-18 Teradyne, Inc. Method of making memory chips using memory tester providing fast repair
US5754556A (en) 1996-07-18 1998-05-19 Teradyne, Inc. Semiconductor memory tester with hardware accelerators
US5764650A (en) 1996-08-02 1998-06-09 Micron Technology, Inc. Intelligent binning for electrically repairable semiconductor chips
US5867505A (en) 1996-08-07 1999-02-02 Micron Technology, Inc. Method and apparatus for testing an integrated circuit including the step/means for storing an associated test identifier in association with integrated circuit identifier for each test to be performed on the integrated circuit
JPH10289597A (en) 1997-04-14 1998-10-27 Advantest Corp Memory testing device
JP2000156095A (en) * 1998-11-19 2000-06-06 Asia Electronics Inc Method and device for testing semiconductor memory
JP3555859B2 (en) * 2000-03-27 2004-08-18 広島日本電気株式会社 Semiconductor production system and semiconductor device production method

Also Published As

Publication number Publication date
WO2001093276A1 (en) 2001-12-06
MY121478A (en) 2006-01-28
KR20030001512A (en) 2003-01-06
TW497193B (en) 2002-08-01
KR100795520B1 (en) 2008-01-16
US6499118B1 (en) 2002-12-24

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