AU2001262871A1 - Optimization of a pipelined processor system - Google Patents

Optimization of a pipelined processor system

Info

Publication number
AU2001262871A1
AU2001262871A1 AU2001262871A AU6287101A AU2001262871A1 AU 2001262871 A1 AU2001262871 A1 AU 2001262871A1 AU 2001262871 A AU2001262871 A AU 2001262871A AU 6287101 A AU6287101 A AU 6287101A AU 2001262871 A1 AU2001262871 A1 AU 2001262871A1
Authority
AU
Australia
Prior art keywords
optimization
processor system
pipelined processor
pipelined
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001262871A
Inventor
Nils Ola Linnermark
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Publication of AU2001262871A1 publication Critical patent/AU2001262871A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
AU2001262871A 2000-09-22 2001-06-01 Optimization of a pipelined processor system Abandoned AU2001262871A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE0003398A SE0003398D0 (en) 2000-09-22 2000-09-22 Optimization of a pipelined processor system
SE0003398 2000-09-22
PCT/SE2001/001234 WO2002025433A1 (en) 2000-09-22 2001-06-01 Optimization of a pipelined processor system

Publications (1)

Publication Number Publication Date
AU2001262871A1 true AU2001262871A1 (en) 2002-04-02

Family

ID=20281128

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001262871A Abandoned AU2001262871A1 (en) 2000-09-22 2001-06-01 Optimization of a pipelined processor system

Country Status (4)

Country Link
US (1) US20030177339A1 (en)
AU (1) AU2001262871A1 (en)
SE (1) SE0003398D0 (en)
WO (1) WO2002025433A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT201700050086A1 (en) * 2017-05-09 2018-11-09 St Microelectronics Srl SAFETY HARDWARE MODULE, ITS PROCESSING SYSTEM, INTEGRATED CIRCUIT, DEVICE AND PROCEDURE

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5255384A (en) * 1985-02-22 1993-10-19 Intergraph Corporation Memory address translation system having modifiable and non-modifiable translation mechanisms
US5287467A (en) * 1991-04-18 1994-02-15 International Business Machines Corporation Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
US5581705A (en) * 1993-12-13 1996-12-03 Cray Research, Inc. Messaging facility with hardware tail pointer and software implemented head pointer message queue for distributed memory massively parallel processing system
US5802288A (en) * 1995-10-26 1998-09-01 International Business Machines Corporation Integrated communications for pipelined computers
US5740391A (en) * 1996-03-01 1998-04-14 Hewlett-Packard Co. Preventing premature early exception signaling with special instruction encoding
US6549930B1 (en) * 1997-11-26 2003-04-15 Compaq Computer Corporation Method for scheduling threads in a multithreaded processor
US6055650A (en) * 1998-04-06 2000-04-25 Advanced Micro Devices, Inc. Processor configured to detect program phase changes and to adapt thereto
US6012134A (en) * 1998-04-09 2000-01-04 Institute For The Development Of Emerging Architectures, L.L.C. High-performance processor with streaming buffer that facilitates prefetching of instructions
US6370622B1 (en) * 1998-11-20 2002-04-09 Massachusetts Institute Of Technology Method and apparatus for curious and column caching
US6442666B1 (en) * 1999-01-28 2002-08-27 Infineon Technologies Ag Techniques for improving memory access in a virtual memory system
US6446197B1 (en) * 1999-10-01 2002-09-03 Hitachi, Ltd. Two modes for executing branch instructions of different lengths and use of branch control instruction and register set loaded with target instructions

Also Published As

Publication number Publication date
SE0003398D0 (en) 2000-09-22
US20030177339A1 (en) 2003-09-18
WO2002025433A1 (en) 2002-03-28

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