AU2001255851A1 - Procedure for worst-case analysis of discrete systems - Google Patents

Procedure for worst-case analysis of discrete systems

Info

Publication number
AU2001255851A1
AU2001255851A1 AU2001255851A AU5585101A AU2001255851A1 AU 2001255851 A1 AU2001255851 A1 AU 2001255851A1 AU 2001255851 A AU2001255851 A AU 2001255851A AU 5585101 A AU5585101 A AU 5585101A AU 2001255851 A1 AU2001255851 A1 AU 2001255851A1
Authority
AU
Australia
Prior art keywords
worst
procedure
case analysis
discrete systems
discrete
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001255851A
Inventor
Felice Balarin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cadence Design Systems Inc
Original Assignee
Cadence Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cadence Design Systems Inc filed Critical Cadence Design Systems Inc
Publication of AU2001255851A1 publication Critical patent/AU2001255851A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/3604—Software analysis for verifying properties of programs
    • G06F11/3608—Software analysis for verifying properties of programs using formal methods, e.g. model checking, abstract interpretation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Debugging And Monitoring (AREA)
AU2001255851A 2000-04-20 2001-04-18 Procedure for worst-case analysis of discrete systems Abandoned AU2001255851A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/552,960 US6397371B1 (en) 2000-04-20 2000-04-20 Procedure for worst-case analysis of discrete systems
US09552960 2000-04-20
PCT/US2001/040543 WO2001082146A1 (en) 2000-04-20 2001-04-18 Procedure for worst-case analysis of discrete systems

Publications (1)

Publication Number Publication Date
AU2001255851A1 true AU2001255851A1 (en) 2001-11-07

Family

ID=24207537

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001255851A Abandoned AU2001255851A1 (en) 2000-04-20 2001-04-18 Procedure for worst-case analysis of discrete systems

Country Status (5)

Country Link
US (1) US6397371B1 (en)
EP (1) EP1282871A4 (en)
JP (1) JP2003533760A (en)
AU (1) AU2001255851A1 (en)
WO (1) WO2001082146A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7401307B2 (en) * 2004-11-03 2008-07-15 International Business Machines Corporation Slack sensitivity to parameter variation based timing analysis
WO2008003427A2 (en) * 2006-07-03 2008-01-10 Inchron Gmbh Method for testing the real-time capability of a system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4924430A (en) * 1988-01-28 1990-05-08 Teradyne, Inc. Static timing analysis of semiconductor digital circuits
US5600576A (en) 1994-03-11 1997-02-04 Northrop Grumman Corporation Time stress measurement device
US5493508A (en) * 1994-06-01 1996-02-20 Lsi Logic Corporation Specification and design of complex digital systems
US5774358A (en) 1996-04-01 1998-06-30 Motorola, Inc. Method and apparatus for generating instruction/data streams employed to verify hardware implementations of integrated circuit designs

Also Published As

Publication number Publication date
EP1282871A1 (en) 2003-02-12
EP1282871A4 (en) 2004-06-30
WO2001082146A1 (en) 2001-11-01
US6397371B1 (en) 2002-05-28
JP2003533760A (en) 2003-11-11

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AU2001255851A1 (en) Procedure for worst-case analysis of discrete systems