AU2001255825A1 - Top/bottom symmetrical protection scheme for flash - Google Patents
Top/bottom symmetrical protection scheme for flashInfo
- Publication number
- AU2001255825A1 AU2001255825A1 AU2001255825A AU5582501A AU2001255825A1 AU 2001255825 A1 AU2001255825 A1 AU 2001255825A1 AU 2001255825 A AU2001255825 A AU 2001255825A AU 5582501 A AU5582501 A AU 5582501A AU 2001255825 A1 AU2001255825 A1 AU 2001255825A1
- Authority
- AU
- Australia
- Prior art keywords
- array
- flash
- memory cells
- protection scheme
- bottom symmetrical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Read Only Memory (AREA)
- Storage Device Security (AREA)
- Medicines That Contain Protein Lipid Enzymes And Other Medicines (AREA)
- Photovoltaic Devices (AREA)
- Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device can comprise an array of memory cells having N addressable sectors, and control circuitry to control erase or write operations on the array of memory cells. Protection circuitry can be coupled to the control circuitry to selectively prevent erase or write operations from being performed on both first and last sectors of the N addressable sectors. The protection circuitry can comprise a multi-bit register having a first bit corresponding to the first sector and a second bit corresponding to the last sector.
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US19350600P | 2000-03-30 | 2000-03-30 | |
US60193506 | 2000-03-30 | ||
US09/608,256 US6654847B1 (en) | 2000-06-30 | 2000-06-30 | Top/bottom symmetrical protection scheme for flash |
US09608256 | 2000-06-30 | ||
PCT/US2001/040413 WO2001075893A2 (en) | 2000-03-30 | 2001-03-30 | Symmetrical protection scheme for first and last sectors of synchronous flash memory |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2001255825A1 true AU2001255825A1 (en) | 2001-10-15 |
Family
ID=26889065
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2001255825A Abandoned AU2001255825A1 (en) | 2000-03-30 | 2001-03-30 | Top/bottom symmetrical protection scheme for flash |
Country Status (7)
Country | Link |
---|---|
EP (2) | EP2287847A3 (en) |
JP (2) | JP3821431B2 (en) |
KR (1) | KR100438636B1 (en) |
AT (1) | ATE479989T1 (en) |
AU (1) | AU2001255825A1 (en) |
DE (2) | DE60142959D1 (en) |
WO (1) | WO2001075893A2 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101024334B1 (en) * | 2003-08-20 | 2011-03-23 | 매그나칩 반도체 유한회사 | Over erase prevention circuit of flash memory device and method therefor |
JP4642017B2 (en) * | 2004-04-13 | 2011-03-02 | スパンション エルエルシー | Sector protection circuit for nonvolatile semiconductor memory device, sector protection method, and nonvolatile semiconductor memory device |
WO2009016824A1 (en) | 2007-08-01 | 2009-02-05 | Panasonic Corporation | Nonvolatile storage device |
JP2012203919A (en) | 2011-03-23 | 2012-10-22 | Toshiba Corp | Semiconductor memory device and control method therefor |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5592641A (en) * | 1993-06-30 | 1997-01-07 | Intel Corporation | Method and device for selectively locking write access to blocks in a memory array using write protect inputs and block enabled status |
US5696917A (en) * | 1994-06-03 | 1997-12-09 | Intel Corporation | Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory |
JP3487690B2 (en) * | 1995-06-20 | 2004-01-19 | シャープ株式会社 | Nonvolatile semiconductor memory device |
US5890191A (en) * | 1996-05-10 | 1999-03-30 | Motorola, Inc. | Method and apparatus for providing erasing and programming protection for electrically erasable programmable read only memory |
US6031757A (en) * | 1996-11-22 | 2000-02-29 | Macronix International Co., Ltd. | Write protected, non-volatile memory device with user programmable sector lock capability |
FR2770327B1 (en) * | 1997-10-24 | 2000-01-14 | Sgs Thomson Microelectronics | ELECTRICALLY PROGRAMMABLE AND ERASABLE NON-VOLATILE MEMORY INCLUDING A PROTECTIVE AREA FOR READING AND / OR WRITING AND ELECTRONIC SYSTEM INCORPORATING THE SAME |
US6026016A (en) * | 1998-05-11 | 2000-02-15 | Intel Corporation | Methods and apparatus for hardware block locking in a nonvolatile memory |
-
2001
- 2001-03-30 JP JP2001573485A patent/JP3821431B2/en not_active Expired - Fee Related
- 2001-03-30 WO PCT/US2001/040413 patent/WO2001075893A2/en active IP Right Grant
- 2001-03-30 KR KR10-2002-7013098A patent/KR100438636B1/en not_active IP Right Cessation
- 2001-03-30 AU AU2001255825A patent/AU2001255825A1/en not_active Abandoned
- 2001-03-30 EP EP10172907A patent/EP2287847A3/en not_active Withdrawn
- 2001-03-30 AT AT01929036T patent/ATE479989T1/en not_active IP Right Cessation
- 2001-03-30 DE DE60142959T patent/DE60142959D1/en not_active Expired - Lifetime
- 2001-03-30 DE DE1269474T patent/DE1269474T1/en active Pending
- 2001-03-30 EP EP01929036A patent/EP1269474B1/en not_active Expired - Lifetime
-
2006
- 2006-01-06 JP JP2006001310A patent/JP4229946B6/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE1269474T1 (en) | 2003-08-14 |
EP2287847A3 (en) | 2011-05-18 |
JP4229946B2 (en) | 2009-02-25 |
JP4229946B6 (en) | 2018-06-27 |
JP3821431B2 (en) | 2006-09-13 |
EP1269474B1 (en) | 2010-09-01 |
EP1269474A2 (en) | 2003-01-02 |
JP2003529881A (en) | 2003-10-07 |
EP2287847A2 (en) | 2011-02-23 |
ATE479989T1 (en) | 2010-09-15 |
KR20020087114A (en) | 2002-11-21 |
WO2001075893A2 (en) | 2001-10-11 |
KR100438636B1 (en) | 2004-07-02 |
JP2006164511A (en) | 2006-06-22 |
DE60142959D1 (en) | 2010-10-14 |
WO2001075893A3 (en) | 2002-04-18 |
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