AU2001253789A1 - Gigabit switch on chip architecture - Google Patents

Gigabit switch on chip architecture

Info

Publication number
AU2001253789A1
AU2001253789A1 AU2001253789A AU5378901A AU2001253789A1 AU 2001253789 A1 AU2001253789 A1 AU 2001253789A1 AU 2001253789 A AU2001253789 A AU 2001253789A AU 5378901 A AU5378901 A AU 5378901A AU 2001253789 A1 AU2001253789 A1 AU 2001253789A1
Authority
AU
Australia
Prior art keywords
data port
data
interface
port interface
management unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001253789A
Inventor
Shekhar Ambe
Shiri Kadambi
Mohan Kalkunte
Govind Malalur
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Publication of AU2001253789A1 publication Critical patent/AU2001253789A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Electronic Switches (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Optical Communication System (AREA)
  • Small-Scale Networks (AREA)
  • Multi Processors (AREA)

Abstract

A data switch for network communications includes a first data port interface which supports at least one data port which transmits and receives data. A second data port interface is also provided supporting at least one data port transmitting and receiving data. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. A common memory is provided, and communicates with the first data port interface and the second data port interface. A memory management unit is provided, and communicates data from the first data port interface and the second data port interface and a common memory. At least two sets of communication channels are provided, with each of the communication channels communicating data and messaging information between the first data port interface, the second data port interface, and the memory management unit. One set of communication channels provides communication from the first and second data port interfaces to the memory management unit and the other set of communication channels provides communication from the memory management unit to the first and second data port interfaces.
AU2001253789A 2000-05-03 2001-04-25 Gigabit switch on chip architecture Abandoned AU2001253789A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US20168500P 2000-05-03 2000-05-03
US60201685 2000-05-03
PCT/US2001/013196 WO2001084327A2 (en) 2000-05-03 2001-04-25 Gigabit switch on chip architecture

Publications (1)

Publication Number Publication Date
AU2001253789A1 true AU2001253789A1 (en) 2001-11-12

Family

ID=22746865

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001253789A Abandoned AU2001253789A1 (en) 2000-05-03 2001-04-25 Gigabit switch on chip architecture

Country Status (5)

Country Link
EP (1) EP1279102B1 (en)
AT (1) ATE330282T1 (en)
AU (1) AU2001253789A1 (en)
DE (1) DE60120684T2 (en)
WO (1) WO2001084327A2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6246680B1 (en) * 1997-06-30 2001-06-12 Sun Microsystems, Inc. Highly integrated multi-layer switch element architecture

Also Published As

Publication number Publication date
ATE330282T1 (en) 2006-07-15
WO2001084327A3 (en) 2002-04-25
EP1279102B1 (en) 2006-06-14
WO2001084327A2 (en) 2001-11-08
EP1279102A2 (en) 2003-01-29
DE60120684D1 (en) 2006-07-27
DE60120684T2 (en) 2007-06-14

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