AU2001253448A1 - Method and apparatus for multi-lane communication channel with deskewing capability - Google Patents

Method and apparatus for multi-lane communication channel with deskewing capability

Info

Publication number
AU2001253448A1
AU2001253448A1 AU2001253448A AU5344801A AU2001253448A1 AU 2001253448 A1 AU2001253448 A1 AU 2001253448A1 AU 2001253448 A AU2001253448 A AU 2001253448A AU 5344801 A AU5344801 A AU 5344801A AU 2001253448 A1 AU2001253448 A1 AU 2001253448A1
Authority
AU
Australia
Prior art keywords
deskewing
capability
communication channel
lane communication
lane
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001253448A
Inventor
Julie A. Giglio
Anne G. O'connell
John G. Ryan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ceva Technologies Ltd
Original Assignee
Parthus Technologies Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Parthus Technologies Ltd filed Critical Parthus Technologies Ltd
Publication of AU2001253448A1 publication Critical patent/AU2001253448A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators
    • H04J3/0629—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators in a network, e.g. in combination with switching or multiplexing, slip buffers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
AU2001253448A 2000-04-11 2001-04-11 Method and apparatus for multi-lane communication channel with deskewing capability Abandoned AU2001253448A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US19646900P 2000-04-11 2000-04-11
US60196469 2000-04-11
US19735200P 2000-04-13 2000-04-13
US60197352 2000-04-13
PCT/US2001/012065 WO2001078337A1 (en) 2000-04-11 2001-04-11 Method and apparatus for multi-lane communication channel with deskewing capability

Publications (1)

Publication Number Publication Date
AU2001253448A1 true AU2001253448A1 (en) 2001-10-23

Family

ID=26891943

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001253448A Abandoned AU2001253448A1 (en) 2000-04-11 2001-04-11 Method and apparatus for multi-lane communication channel with deskewing capability

Country Status (3)

Country Link
US (1) US20020018444A1 (en)
AU (1) AU2001253448A1 (en)
WO (1) WO2001078337A1 (en)

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US5978379A (en) 1997-01-23 1999-11-02 Gadzoox Networks, Inc. Fiber channel learning bridge, learning half bridge, and protocol
US7430171B2 (en) 1998-11-19 2008-09-30 Broadcom Corporation Fibre channel arbitrated loop bufferless switch circuitry to increase bandwidth without significant increase in cost
US6509773B2 (en) * 2000-04-28 2003-01-21 Broadcom Corporation Phase interpolator device and method
US6690757B1 (en) * 2000-06-20 2004-02-10 Hewlett-Packard Development Company, L.P. High-speed interconnection adapter having automated lane de-skew
US7231008B2 (en) * 2002-11-15 2007-06-12 Vitesse Semiconductor Corporation Fast locking clock and data recovery unit
US7551645B2 (en) * 2003-01-31 2009-06-23 Broadcom Corporation Apparatus and method to receive and align incoming data including SPI data in a buffer to expand data width by utilizing a single read port and single write port memory device
TWI249681B (en) * 2003-07-02 2006-02-21 Via Tech Inc Circuit and method for aligning data transmitting timing of a plurality of lanes
US7672335B2 (en) * 2003-12-10 2010-03-02 Intel Corporation Non-integer word size translation through rotation of different buffer alignment channels
US7549074B2 (en) * 2005-06-02 2009-06-16 Agere Systems Inc. Content deskewing for multichannel synchronization
US7697529B2 (en) * 2006-02-28 2010-04-13 Cisco Technology, Inc. Fabric channel control apparatus and method
EP2060044A2 (en) * 2006-08-29 2009-05-20 Koninklijke Philips Electronics N.V. Method and apparatus for high speed lvds communication
US9014563B2 (en) * 2006-12-11 2015-04-21 Cisco Technology, Inc. System and method for providing an Ethernet interface
WO2009075713A1 (en) 2007-12-06 2009-06-18 Rambus, Inc. Apparatus and methods for differential signal receiving
US8036248B2 (en) * 2008-10-29 2011-10-11 Silicon Image, Inc. Method, apparatus, and system for automatic data aligner for multiple serial receivers
WO2011043398A1 (en) * 2009-10-09 2011-04-14 三菱電機株式会社 Differential encoding optical transceiver device
US8483344B2 (en) 2011-06-13 2013-07-09 Stephen C. Dillinger Fast lock serializer-deserializer (SERDES) architecture
US8971352B2 (en) * 2012-09-28 2015-03-03 Thomas Jost High accuracy 1588 timestamping over high speed multi lane distribution physical code sublayers
US9705777B2 (en) * 2013-02-08 2017-07-11 Macom Connectivity Solutions, Llc System and method for monitoring encoded signals in a network
US8947140B2 (en) * 2013-03-12 2015-02-03 Uniquify, Inc. Continuous adaptive training for data interface timing calibration
US11334509B2 (en) 2013-03-12 2022-05-17 Uniquify, Inc. Continuous adaptive data capture optimization for interface circuits
US9658643B2 (en) * 2014-10-24 2017-05-23 Samsung Electronics Co., Ltd. Data interface and data transmission method
US10581587B1 (en) * 2019-04-29 2020-03-03 Advanced Micro Devices, Inc. Deskewing method for a physical layer interface on a multi-chip module

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4979169A (en) * 1989-02-14 1990-12-18 Data General Corporation Method and apparatus for performing format conversion between bit streams
US5978831A (en) * 1991-03-07 1999-11-02 Lucent Technologies Inc. Synchronous multiprocessor using tasks directly proportional in size to the individual processors rates
WO1994011955A1 (en) * 1992-11-06 1994-05-26 Pericle Communications Company Adaptive data rate modem
SE515335C2 (en) * 1993-09-14 2001-07-16 Nec Corp Speed conversion device which can determine a transmission rate as desired
US5761200A (en) * 1993-10-27 1998-06-02 Industrial Technology Research Institute Intelligent distributed data transfer system
EP0730380B1 (en) * 1994-09-16 2004-03-03 Sony Corporation Data output device and data output method
US5999563A (en) * 1996-05-09 1999-12-07 Texas Instruments Incorporated Rate negotiation for variable-rate digital subscriber line signaling
US6456782B1 (en) * 1997-12-27 2002-09-24 Sony Corporation Data processing device and method for the same
JP3147078B2 (en) * 1998-04-06 2001-03-19 日本電気株式会社 Apparatus and apparatus for removing dummy bits of FEC code word
US7386008B2 (en) * 2001-07-19 2008-06-10 Eci Telecom Ltd. Method and apparatus for converting data packets between a higher bandwidth network and a lower bandwidth network having multiple channels

Also Published As

Publication number Publication date
US20020018444A1 (en) 2002-02-14
WO2001078337A1 (en) 2001-10-18

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