AU2001249643A1 - Multi-channel, multi-service debug on a pipelined cpu architecture - Google Patents

Multi-channel, multi-service debug on a pipelined cpu architecture

Info

Publication number
AU2001249643A1
AU2001249643A1 AU2001249643A AU4964301A AU2001249643A1 AU 2001249643 A1 AU2001249643 A1 AU 2001249643A1 AU 2001249643 A AU2001249643 A AU 2001249643A AU 4964301 A AU4964301 A AU 4964301A AU 2001249643 A1 AU2001249643 A1 AU 2001249643A1
Authority
AU
Australia
Prior art keywords
channel
cpu architecture
pipelined cpu
executing service
service
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001249643A
Inventor
Kelly Gene Johnson
Mark Williams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Publication of AU2001249643A1 publication Critical patent/AU2001249643A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3628—Software debugging of optimised code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3648—Software debugging using additional hardware

Abstract

A method and system for debugging an executing service on a pipelined CPU architecture are described. In one embodiment, a breakpoint within an executing service is set and a minimum state of the executing service is saved. In addition, a program counter of the executing service is altered. The program counter is restored and the state of the executing service is restored.
AU2001249643A 2000-03-30 2001-03-30 Multi-channel, multi-service debug on a pipelined cpu architecture Abandoned AU2001249643A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09539197 2000-03-30
US09/539,197 US6934937B1 (en) 2000-03-30 2000-03-30 Multi-channel, multi-service debug on a pipelined CPU architecture
PCT/US2001/010251 WO2001075605A2 (en) 2000-03-30 2001-03-30 Multi-channel, multi-service debug on a pipelined cpu architecture

Publications (1)

Publication Number Publication Date
AU2001249643A1 true AU2001249643A1 (en) 2001-10-15

Family

ID=24150210

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001249643A Abandoned AU2001249643A1 (en) 2000-03-30 2001-03-30 Multi-channel, multi-service debug on a pipelined cpu architecture

Country Status (6)

Country Link
US (2) US6934937B1 (en)
EP (1) EP1269322B1 (en)
AT (1) ATE289096T1 (en)
AU (1) AU2001249643A1 (en)
DE (1) DE60108851T2 (en)
WO (1) WO2001075605A2 (en)

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Also Published As

Publication number Publication date
DE60108851T2 (en) 2006-01-05
US6934937B1 (en) 2005-08-23
US7565644B2 (en) 2009-07-21
ATE289096T1 (en) 2005-02-15
EP1269322B1 (en) 2005-02-09
WO2001075605A3 (en) 2002-03-14
DE60108851D1 (en) 2005-03-17
US20050188358A1 (en) 2005-08-25
EP1269322A2 (en) 2003-01-02
WO2001075605A2 (en) 2001-10-11

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