AU2001247270A1 - Method and apparatus for facilitating exception handling using a conditional trap instruction - Google Patents

Method and apparatus for facilitating exception handling using a conditional trap instruction

Info

Publication number
AU2001247270A1
AU2001247270A1 AU2001247270A AU4727001A AU2001247270A1 AU 2001247270 A1 AU2001247270 A1 AU 2001247270A1 AU 2001247270 A AU2001247270 A AU 2001247270A AU 4727001 A AU4727001 A AU 4727001A AU 2001247270 A1 AU2001247270 A1 AU 2001247270A1
Authority
AU
Australia
Prior art keywords
exception handling
trap instruction
conditional trap
facilitating
facilitating exception
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001247270A
Inventor
Shailender Chaudhry
Marc Tremblay
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of AU2001247270A1 publication Critical patent/AU2001247270A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Devices For Executing Special Programs (AREA)
AU2001247270A 2000-03-06 2001-03-01 Method and apparatus for facilitating exception handling using a conditional trap instruction Abandoned AU2001247270A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US18697900P 2000-03-06 2000-03-06
US60186979 2000-03-06
US09/591,142 US6704862B1 (en) 2000-03-06 2000-06-09 Method and apparatus for facilitating exception handling using a conditional trap instruction
US09591142 2000-06-09
PCT/US2001/006931 WO2001067239A2 (en) 2000-03-06 2001-03-01 Method and apparatus for facilitating exception handling using a conditional trap instruction

Publications (1)

Publication Number Publication Date
AU2001247270A1 true AU2001247270A1 (en) 2001-09-17

Family

ID=26882618

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001247270A Abandoned AU2001247270A1 (en) 2000-03-06 2001-03-01 Method and apparatus for facilitating exception handling using a conditional trap instruction

Country Status (3)

Country Link
US (1) US6704862B1 (en)
AU (1) AU2001247270A1 (en)
WO (1) WO2001067239A2 (en)

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JP3974742B2 (en) * 2000-04-14 2007-09-12 インターナショナル・ビジネス・マシーンズ・コーポレーション Compile device, optimization method, and recording medium
US6681317B1 (en) * 2000-09-29 2004-01-20 Intel Corporation Method and apparatus to provide advanced load ordering
US20020199179A1 (en) * 2001-06-21 2002-12-26 Lavery Daniel M. Method and apparatus for compiler-generated triggering of auxiliary codes
CA2383832A1 (en) * 2002-04-24 2003-10-24 Ibm Canada Limited-Ibm Canada Limitee System and method for intelligent trap analysis
US7178136B2 (en) * 2003-06-30 2007-02-13 International Business Machines Corporation Debugging step-back button
US7770169B2 (en) * 2004-05-17 2010-08-03 Oracle America, Inc. Thread rendezvous for read-only code in an object-oriented computing environment
JP2005338987A (en) * 2004-05-25 2005-12-08 Fujitsu Ltd Exception test support program and device
US7698697B2 (en) * 2005-03-03 2010-04-13 International Business Machines Corporation Transforming code to expose glacial constants to a compiler
US7840950B2 (en) * 2006-03-09 2010-11-23 International Business Machines Corporation Programmatic compiler optimization of glacial constants
US7747899B2 (en) * 2007-06-26 2010-06-29 Microsoft Corporation Providing mapping fault processing
US8566780B2 (en) * 2007-06-26 2013-10-22 Microsoft Corporation Object model based mapping
US10387151B2 (en) 2007-12-31 2019-08-20 Intel Corporation Processor and method for tracking progress of gathering/scattering data element pairs in different cache memory banks
US7984273B2 (en) 2007-12-31 2011-07-19 Intel Corporation System and method for using a mask register to track progress of gathering elements from memory
US8447962B2 (en) * 2009-12-22 2013-05-21 Intel Corporation Gathering and scattering multiple data elements
CN101482831B (en) * 2008-01-08 2013-05-15 国际商业机器公司 Method and equipment for concomitant scheduling of working thread and worker thread
US8239843B2 (en) * 2008-03-11 2012-08-07 Oracle America, Inc. Value predictable variable scoping for speculative automatic parallelization with transactional memory
US10175990B2 (en) 2009-12-22 2019-01-08 Intel Corporation Gathering and scattering multiple data elements
US8782434B1 (en) 2010-07-15 2014-07-15 The Research Foundation For The State University Of New York System and method for validating program execution at run-time
US9626333B2 (en) 2012-06-02 2017-04-18 Intel Corporation Scatter using index array and finite state machine
US8972697B2 (en) 2012-06-02 2015-03-03 Intel Corporation Gather using index array and finite state machine
US9063721B2 (en) 2012-09-14 2015-06-23 The Research Foundation For The State University Of New York Continuous run-time validation of program execution: a practical approach
US9069782B2 (en) 2012-10-01 2015-06-30 The Research Foundation For The State University Of New York System and method for security and privacy aware virtual machine checkpointing
JP6608322B2 (en) * 2016-03-31 2019-11-20 株式会社沖データ Optical print head and image forming apparatus

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0816871B2 (en) 1990-12-07 1996-02-21 富士ゼロックス株式会社 Program translation device and program translation method
US5778219A (en) 1990-12-14 1998-07-07 Hewlett-Packard Company Method and system for propagating exception status in data registers and for detecting exceptions from speculative operations with non-speculative operations
US5634023A (en) 1994-07-01 1997-05-27 Digital Equipment Corporation Software mechanism for accurately handling exceptions generated by speculatively scheduled instructions
US5835776A (en) 1995-11-17 1998-11-10 Sun Microsystems, Inc. Method and apparatus for instruction scheduling in an optimizing compiler for minimizing overhead instructions
US5802337A (en) 1995-12-29 1998-09-01 Intel Corporation Method and apparatus for executing load instructions speculatively
US5815719A (en) 1996-05-07 1998-09-29 Sun Microsystems, Inc. Method and apparatus for easy insertion of assembler code for optimization
EP1031076A1 (en) 1997-10-13 2000-08-30 Institute for the Development of Emerging Architectures, L.L.C. Method and apparatus for optimizing execution of load and store instructions
US6301705B1 (en) 1998-10-01 2001-10-09 Institute For The Development Of Emerging Architectures, L.L.C. System and method for deferring exceptions generated during speculative execution
US6487716B1 (en) 1999-10-08 2002-11-26 International Business Machines Corporation Methods and apparatus for optimizing programs in the presence of exceptions

Also Published As

Publication number Publication date
US6704862B1 (en) 2004-03-09
WO2001067239A3 (en) 2002-05-02
WO2001067239A2 (en) 2001-09-13

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