AU2001245833A1 - Method and apparatus for adding user-defined execution units to a processor using configurable long instruction word (cliw) - Google Patents

Method and apparatus for adding user-defined execution units to a processor using configurable long instruction word (cliw)

Info

Publication number
AU2001245833A1
AU2001245833A1 AU2001245833A AU4583301A AU2001245833A1 AU 2001245833 A1 AU2001245833 A1 AU 2001245833A1 AU 2001245833 A AU2001245833 A AU 2001245833A AU 4583301 A AU4583301 A AU 4583301A AU 2001245833 A1 AU2001245833 A1 AU 2001245833A1
Authority
AU
Australia
Prior art keywords
cliw
processor
execution units
instruction word
long instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001245833A
Inventor
Haim Granot
Regis Hervigo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of AU2001245833A1 publication Critical patent/AU2001245833A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30196—Instruction operation extension or modification using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
AU2001245833A 2000-03-27 2001-03-16 Method and apparatus for adding user-defined execution units to a processor using configurable long instruction word (cliw) Abandoned AU2001245833A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US19240300P 2000-03-27 2000-03-27
US60192403 2000-03-27
PCT/US2001/008583 WO2001073571A1 (en) 2000-03-27 2001-03-16 Method and apparatus for adding user-defined execution units to a processor using configurable long instruction word (cliw)

Publications (1)

Publication Number Publication Date
AU2001245833A1 true AU2001245833A1 (en) 2001-10-08

Family

ID=22709493

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001245833A Abandoned AU2001245833A1 (en) 2000-03-27 2001-03-16 Method and apparatus for adding user-defined execution units to a processor using configurable long instruction word (cliw)

Country Status (6)

Country Link
US (1) US7043625B2 (en)
EP (1) EP1269333A4 (en)
JP (1) JP2003529151A (en)
CN (1) CN1227601C (en)
AU (1) AU2001245833A1 (en)
WO (1) WO2001073571A1 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6691190B1 (en) * 2000-01-24 2004-02-10 Agere Systems Inc. Inter-DSP data exchange in a multiple DSP environment
US7376812B1 (en) 2002-05-13 2008-05-20 Tensilica, Inc. Vector co-processor for configurable and extensible processor architecture
US7346881B2 (en) 2002-05-13 2008-03-18 Tensilica, Inc. Method and apparatus for adding advanced instructions in an extensible processor architecture
US7937559B1 (en) 2002-05-13 2011-05-03 Tensilica, Inc. System and method for generating a configurable processor supporting a user-defined plurality of instruction sizes
DE102004025418A1 (en) * 2004-05-24 2005-12-22 Infineon Technologies Ag Controller with a decoder
US7689402B2 (en) 2006-11-17 2010-03-30 Telefonaktiebolaget Lm Ericsson (Publ) Method and apparatus for retrieving application-specific code using memory access capabilities of a host processor
GB2462860B (en) 2008-08-22 2012-05-16 Advanced Risc Mach Ltd Apparatus and method for communicating between a central processing unit and a graphics processing unit
CN102033736A (en) * 2010-12-31 2011-04-27 清华大学 Control method for instruction set expandable processor
CN102520907A (en) * 2011-12-13 2012-06-27 杭州晟元芯片技术有限公司 Software and hardware integrated accelerator and implementation method for same
US9396056B2 (en) * 2014-03-15 2016-07-19 Intel Corporation Conditional memory fault assist suppression
US9870339B2 (en) * 2015-06-26 2018-01-16 Intel Corporation Hardware processors and methods for tightly-coupled heterogeneous computing
CN106371807B (en) * 2016-08-30 2019-03-19 华为技术有限公司 A kind of method and device of extensible processor instruction set

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5848289A (en) * 1992-11-27 1998-12-08 Motorola, Inc. Extensible central processing unit
JP3623840B2 (en) 1996-01-31 2005-02-23 株式会社ルネサステクノロジ Data processing apparatus and microprocessor
US5805875A (en) * 1996-09-13 1998-09-08 International Computer Science Institute Vector processing system with multi-operation, run-time configurable pipelines
US6026478A (en) * 1997-08-01 2000-02-15 Micron Technology, Inc. Split embedded DRAM processor
US6173389B1 (en) * 1997-12-04 2001-01-09 Billions Of Operations Per Second, Inc. Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor
EP0942359B1 (en) 1998-02-19 2012-07-04 Lantiq Deutschland GmbH An apparatus for executing instructions of a program

Also Published As

Publication number Publication date
WO2001073571A1 (en) 2001-10-04
EP1269333A1 (en) 2003-01-02
US7043625B2 (en) 2006-05-09
EP1269333A4 (en) 2007-01-03
JP2003529151A (en) 2003-09-30
CN1411578A (en) 2003-04-16
CN1227601C (en) 2005-11-16
US20010037441A1 (en) 2001-11-01

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