AU2001241897A1 - Device level layout optimization in electronic design automation - Google Patents

Device level layout optimization in electronic design automation

Info

Publication number
AU2001241897A1
AU2001241897A1 AU2001241897A AU4189701A AU2001241897A1 AU 2001241897 A1 AU2001241897 A1 AU 2001241897A1 AU 2001241897 A AU2001241897 A AU 2001241897A AU 4189701 A AU4189701 A AU 4189701A AU 2001241897 A1 AU2001241897 A1 AU 2001241897A1
Authority
AU
Australia
Prior art keywords
device level
electronic design
design automation
layout optimization
level layout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001241897A
Inventor
Bogdan Arsintescu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cadence Design Systems Inc
Original Assignee
Cadence Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cadence Design Systems Inc filed Critical Cadence Design Systems Inc
Publication of AU2001241897A1 publication Critical patent/AU2001241897A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
AU2001241897A 2000-02-29 2001-02-28 Device level layout optimization in electronic design automation Abandoned AU2001241897A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US18582600P 2000-02-29 2000-02-29
US60/185,826 2000-02-29
US09/797,386 US6671866B2 (en) 2000-02-29 2001-02-28 Device level layout optimization in electronic design automation
US09/797,386 2001-02-28
PCT/US2001/006610 WO2001065424A2 (en) 2000-02-29 2001-02-28 Device level layout optimization in electronic design automation

Publications (1)

Publication Number Publication Date
AU2001241897A1 true AU2001241897A1 (en) 2001-09-12

Family

ID=26881509

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001241897A Abandoned AU2001241897A1 (en) 2000-02-29 2001-02-28 Device level layout optimization in electronic design automation

Country Status (3)

Country Link
US (1) US6671866B2 (en)
AU (1) AU2001241897A1 (en)
WO (1) WO2001065424A2 (en)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6820247B1 (en) * 2000-06-14 2004-11-16 Advanced Micro Devices, Inc. Method and apparatus for constructing a global interconnect model of a device having ambiguous submodule abutments
US7103863B2 (en) * 2001-06-08 2006-09-05 Magma Design Automation, Inc. Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system
US8082138B1 (en) * 2002-04-11 2011-12-20 Synopsys, Inc. Automated bottom-up and top-down partitioned design synthesis
US6711730B2 (en) 2002-05-13 2004-03-23 Hewlett-Packard Development Company, L.P. Synthesizing signal net information from multiple integrated circuit package models
JP4320413B2 (en) * 2002-09-11 2009-08-26 日本電気株式会社 Semiconductor integrated circuit and layout design apparatus
US7269817B2 (en) 2004-02-10 2007-09-11 International Business Machines Corporation Lithographic process window optimization under complex constraints on edge placement
US10215562B2 (en) * 2004-07-16 2019-02-26 Invention Science Find I, LLC Personalized prototyping
US7806339B2 (en) * 2004-03-16 2010-10-05 The Invention Science Fund I, Llc Embedded identifiers
US20060012081A1 (en) * 2004-07-16 2006-01-19 Bran Ferren Custom prototyping
US20060025878A1 (en) * 2004-07-30 2006-02-02 Bran Ferren Interior design using rapid prototyping
US20060031044A1 (en) * 2004-08-04 2006-02-09 Bran Ferren Identification of interior design features
US20060004476A1 (en) * 2004-07-02 2006-01-05 Bran Ferren System for making custom prototypes
US7664563B2 (en) 2007-09-14 2010-02-16 Searete Llc System for making custom prototypes
US7600208B1 (en) 2007-01-31 2009-10-06 Cadence Design Systems, Inc. Automatic placement of decoupling capacitors
US8713493B2 (en) * 2007-12-21 2014-04-29 Cadence Design Systems, Inc. System and method for solving connection violations
US8103990B2 (en) * 2008-02-28 2012-01-24 Arm Limited Characterising circuit cell performance variability in response to perturbations in manufacturing process parameters
US8677278B2 (en) * 2008-08-01 2014-03-18 Autodesk, Inc. Package data format
US8316334B2 (en) * 2010-02-04 2012-11-20 Qualcomm Incorporated Segment and bipartite graph based apparatus and method to address hold violations in static timing
US8539388B2 (en) * 2010-07-14 2013-09-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for low power semiconductor chip layout and low power semiconductor chip
US8977863B1 (en) 2010-08-30 2015-03-10 Cadence Design Systems, Inc. Methods, systems, and articles of manufacture for dynamic protection of intellectual property in electronic circuit designs
US8742464B2 (en) 2011-03-03 2014-06-03 Synopsys, Inc. Power routing in standard cells
US8612914B2 (en) 2011-03-23 2013-12-17 Synopsys, Inc. Pin routing in standard cells
US8513978B2 (en) 2011-03-30 2013-08-20 Synopsys, Inc. Power routing in standard cell designs
US8631374B2 (en) 2011-03-30 2014-01-14 Synopsys, Inc. Cell architecture for increasing transistor size
US8386982B1 (en) * 2011-06-13 2013-02-26 Cadence Design Systems, Inc. System, method, and computer program product for pin assignment in an electronic design
US8719754B1 (en) 2011-08-31 2014-05-06 Cadence Design Systems, Inc. System and method to generate re-useable layout components from schematic components in an IC design with hierarchical parameters
US8464194B1 (en) * 2011-12-16 2013-06-11 International Business Machines Corporation Machine learning approach to correct lithographic hot-spots
US9507909B2 (en) * 2012-10-12 2016-11-29 The Boeing Company System and method for computational planning in a data-dependent constraint management system
US8694941B1 (en) 2012-06-01 2014-04-08 Cadence Design Systems, Inc. System and method for abutment in the presence of dummy shapes
US9830414B2 (en) * 2014-06-16 2017-11-28 Raytheon Company Pattern matching techniques in analog and mixed signal circuits
CN113435158B (en) * 2021-07-14 2022-05-24 成都华大九天科技有限公司 Method for rebuilding parallel substructure of circuit

Also Published As

Publication number Publication date
WO2001065424A3 (en) 2003-01-23
WO2001065424A2 (en) 2001-09-07
US6671866B2 (en) 2003-12-30
US20010034873A1 (en) 2001-10-25

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