AU2001241486A1 - System including cpu and code translator for translating code from a second instruction set to a first instruction set executable by the cpu - Google Patents

System including cpu and code translator for translating code from a second instruction set to a first instruction set executable by the cpu

Info

Publication number
AU2001241486A1
AU2001241486A1 AU2001241486A AU4148601A AU2001241486A1 AU 2001241486 A1 AU2001241486 A1 AU 2001241486A1 AU 2001241486 A AU2001241486 A AU 2001241486A AU 4148601 A AU4148601 A AU 4148601A AU 2001241486 A1 AU2001241486 A1 AU 2001241486A1
Authority
AU
Australia
Prior art keywords
instruction set
cpu
code
system including
translating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001241486A
Inventor
John E. Derrick
Robert G. Mcdonald
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Chicory Systems Inc
Original Assignee
Chicory Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chicory Systems Inc filed Critical Chicory Systems Inc
Publication of AU2001241486A1 publication Critical patent/AU2001241486A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
    • G06F9/45516—Runtime code conversion or optimisation
    • G06F9/4552—Involving translation to a different instruction set architecture, e.g. just-in-time translation in a JVM

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
AU2001241486A 2000-02-14 2001-02-13 System including cpu and code translator for translating code from a second instruction set to a first instruction set executable by the cpu Abandoned AU2001241486A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US50592700A 2000-02-14 2000-02-14
US09505927 2000-02-14
PCT/US2001/004742 WO2001061476A2 (en) 2000-02-14 2001-02-13 System including cpu and code translator for translating code from a second instruction set to a first instruction set

Publications (1)

Publication Number Publication Date
AU2001241486A1 true AU2001241486A1 (en) 2001-08-27

Family

ID=24012458

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001241486A Abandoned AU2001241486A1 (en) 2000-02-14 2001-02-13 System including cpu and code translator for translating code from a second instruction set to a first instruction set executable by the cpu

Country Status (2)

Country Link
AU (1) AU2001241486A1 (en)
WO (1) WO2001061476A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2376100B (en) * 2001-05-31 2005-03-09 Advanced Risc Mach Ltd Data processing using multiple instruction sets

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5768593A (en) * 1996-03-22 1998-06-16 Connectix Corporation Dynamic cross-compilation system and method
US6011908A (en) * 1996-12-23 2000-01-04 Transmeta Corporation Gated store buffer for an advanced microprocessor
AU745449B2 (en) * 1997-11-20 2002-03-21 Hajime Seki Computer system
WO2001061477A1 (en) * 2000-02-14 2001-08-23 Chicory Systems, Inc. Predecoding instructions to determine stack change information

Also Published As

Publication number Publication date
WO2001061476A3 (en) 2002-05-02
WO2001061476A2 (en) 2001-08-23

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