AU2000264193A1 - A method and apparatus for simultaneous differential data sensing and capture ina high speed memory - Google Patents

A method and apparatus for simultaneous differential data sensing and capture ina high speed memory

Info

Publication number
AU2000264193A1
AU2000264193A1 AU2000264193A AU6419300A AU2000264193A1 AU 2000264193 A1 AU2000264193 A1 AU 2000264193A1 AU 2000264193 A AU2000264193 A AU 2000264193A AU 6419300 A AU6419300 A AU 6419300A AU 2000264193 A1 AU2000264193 A1 AU 2000264193A1
Authority
AU
Australia
Prior art keywords
capture
high speed
differential data
speed memory
data sensing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2000264193A
Inventor
Paul Demone
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Publication of AU2000264193A1 publication Critical patent/AU2000264193A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
AU2000264193A 2000-07-07 2000-07-31 A method and apparatus for simultaneous differential data sensing and capture ina high speed memory Abandoned AU2000264193A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CA002313948A CA2313948A1 (en) 2000-07-07 2000-07-07 Low delay, conditional differential data sense and capture scheme for a high speed dram
CA2313948 2000-07-07
PCT/CA2000/000879 WO2002005282A1 (en) 2000-07-07 2000-07-31 A method and apparatus for simultaneous differential data sensing and capture in a high speed memory

Publications (1)

Publication Number Publication Date
AU2000264193A1 true AU2000264193A1 (en) 2002-01-21

Family

ID=4166719

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2000264193A Abandoned AU2000264193A1 (en) 2000-07-07 2000-07-31 A method and apparatus for simultaneous differential data sensing and capture ina high speed memory

Country Status (7)

Country Link
US (1) US7269075B2 (en)
JP (1) JP2004502268A (en)
KR (1) KR100816939B1 (en)
CN (2) CN101441888B (en)
AU (1) AU2000264193A1 (en)
CA (1) CA2313948A1 (en)
WO (1) WO2002005282A1 (en)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100869870B1 (en) 2000-07-07 2008-11-24 모사이드 테크놀로지스, 인코포레이티드 A method for performing a read command in a memory device and a method for accessing dram
US7071737B2 (en) * 2004-07-13 2006-07-04 Kabushiki Kaisha Toshiba Systems and methods for controlling timing in a circuit
US7907456B2 (en) * 2007-10-31 2011-03-15 Texas Instruments Incorporated Memory having circuitry controlling the voltage differential between the word line and array supply voltage
KR100967386B1 (en) * 2008-05-07 2010-07-05 주식회사 케이디파워 Busbar connecting clip
KR200451968Y1 (en) * 2008-07-14 2011-01-25 심상민 Bus-bar connector
KR100956783B1 (en) * 2008-10-14 2010-05-12 주식회사 하이닉스반도체 Semiconductor Memory Apparatus
US8242823B2 (en) 2009-04-27 2012-08-14 Oracle America, Inc. Delay chain initialization
US8283960B2 (en) * 2009-04-27 2012-10-09 Oracle America, Inc. Minimal bubble voltage regulator
US8179165B2 (en) * 2009-04-27 2012-05-15 Oracle America, Inc. Precision sampling circuit
KR101111972B1 (en) * 2009-12-04 2012-02-14 김계수 Distribution Booth Bar
US9911470B2 (en) * 2011-12-15 2018-03-06 Nvidia Corporation Fast-bypass memory circuit
US10141930B2 (en) 2013-06-04 2018-11-27 Nvidia Corporation Three state latch
US9997232B2 (en) 2016-03-10 2018-06-12 Micron Technology, Inc. Processing in memory (PIM) capable memory device having sensing circuitry performing logic operations
US10395704B2 (en) 2017-12-22 2019-08-27 Micron Technology, Inc. Apparatuses and methods for duty cycle error correction of clock signals
US10249354B1 (en) 2018-02-23 2019-04-02 Micron Technology, Inc. Apparatuses and methods for duty cycle distortion correction of clocks
KR20210000740A (en) 2018-05-29 2021-01-05 마이크론 테크놀로지, 인크. Apparatus and method for setting duty cycle adjuster for improving clock duty cycle
US10715127B2 (en) 2018-11-21 2020-07-14 Micron Technology, Inc. Apparatuses and methods for using look-ahead duty cycle correction to determine duty cycle adjustment values while a semiconductor device remains in operation
US11189334B2 (en) 2018-11-21 2021-11-30 Micron Technology, Inc. Apparatuses and methods for a multi-bit duty cycle monitor
CN112712833A (en) * 2019-10-25 2021-04-27 长鑫存储技术(上海)有限公司 Write operation circuit, semiconductor memory and write operation method
CN116092549B (en) * 2023-01-16 2023-08-18 浙江力积存储科技有限公司 Storage structure

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5297092A (en) * 1992-06-03 1994-03-22 Mips Computer Systems, Inc. Sense amp for bit line sensing and data latching
US5485430A (en) * 1992-12-22 1996-01-16 Sgs-Thomson Microelectronics, Inc. Multiple clocked dynamic sense amplifier
US5452239A (en) * 1993-01-29 1995-09-19 Quickturn Design Systems, Inc. Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system
JPH08250997A (en) * 1995-03-14 1996-09-27 Fujitsu Ltd Input circuit
US5977798A (en) * 1997-02-28 1999-11-02 Rambus Incorporated Low-latency small-swing clocked receiver
JPH10327066A (en) * 1997-05-27 1998-12-08 Sony Corp Nmos gate input sense amplifier in transistor logic circuit
US5977789A (en) * 1997-08-27 1999-11-02 Intel Corporation Fast-switching logic gate
JP3488612B2 (en) * 1997-12-11 2004-01-19 株式会社東芝 Sense amplifier circuit
JP4057125B2 (en) * 1998-01-23 2008-03-05 株式会社ルネサステクノロジ Semiconductor memory device
US6201418B1 (en) * 1998-08-13 2001-03-13 Compaq Computer Corporation Differential sense amplifier with reduced hold time
US5959899A (en) * 1998-08-25 1999-09-28 Mosel Vitelic Corporation Semiconductor memory having single path data pipeline for CAS-latency
KR100304195B1 (en) * 1998-09-18 2001-11-22 윤종용 Synchronous Semiconductor Memory Device with External Clock Signal
JP3510507B2 (en) * 1998-11-27 2004-03-29 Ｎｅｃマイクロシステム株式会社 Latch circuit

Also Published As

Publication number Publication date
WO2002005282A1 (en) 2002-01-17
US7269075B2 (en) 2007-09-11
CN1454384A (en) 2003-11-05
JP2004502268A (en) 2004-01-22
US20030156461A1 (en) 2003-08-21
CN101441888A (en) 2009-05-27
KR100816939B1 (en) 2008-03-26
CN101441888B (en) 2011-10-19
CA2313948A1 (en) 2002-01-07
KR20030045771A (en) 2003-06-11

Similar Documents

Publication Publication Date Title
AU2000264193A1 (en) A method and apparatus for simultaneous differential data sensing and capture ina high speed memory
AU2001293170A1 (en) Method and apparatus for linking data and objects
AU2001257586A1 (en) Apparatus and method for gathering and utilizing data
AU2002220172A1 (en) Apparatus and method for organizing and/or presenting data
AU2002355090A1 (en) Apparatus and method for seismic data acquisition
AU2001287927A1 (en) A data processing apparatus and method for saving return state
AU2001272094A1 (en) Data transfer method and apparatus
AU7209501A (en) Data transfer method and apparatus
AU2001239907A1 (en) Method and apparatus for building a memory image
AU2001247883A1 (en) Seismic data processing method
AU2001280757A1 (en) Method and apparatus for analyzing financial data
AU2001285098A1 (en) Method and apparatus for writing data in a disk drive
AU2002215496A1 (en) Method and apparatus for routing program data in a program viewing unit
EP1271514A4 (en) Data recording method and data recording apparatus
AU2001291204A1 (en) Data synchronization method and apparatus
AU2002221394A1 (en) Method and apparatus for reducing latency in a memory system
AU2002241635A1 (en) A method and apparatus for transforming data
GB0002181D0 (en) Method and apparatus for processing configuration-sensitive data
AUPR323001A0 (en) An apparatus and method for detecting an object in a medium
IL133790A0 (en) Data signal for modifying a graphic scene, corresponding method and device
AU2001269903A1 (en) Block-level read while write method and apparatus
AU2001255229A1 (en) Method and apparatus for overlaying memory in a data processing system
AU7843400A (en) Apparatus and method for reading/writing data from/to a storage device having multiple storage areas
SG102632A1 (en) Data recovery apparatus and method
AU2002221633A1 (en) Method and device for capturing production data from a production plant