AU1952883A - Circuit arrangement for universally usable buffer storage - Google Patents

Circuit arrangement for universally usable buffer storage

Info

Publication number
AU1952883A
AU1952883A AU19528/83A AU1952883A AU1952883A AU 1952883 A AU1952883 A AU 1952883A AU 19528/83 A AU19528/83 A AU 19528/83A AU 1952883 A AU1952883 A AU 1952883A AU 1952883 A AU1952883 A AU 1952883A
Authority
AU
Australia
Prior art keywords
circuit arrangement
buffer storage
universally usable
usable buffer
universally
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU19528/83A
Inventor
Reinhart Pfingst
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PFINGST R
Original Assignee
PFINGST R
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PFINGST R filed Critical PFINGST R
Publication of AU1952883A publication Critical patent/AU1952883A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/06—Indexing scheme relating to groups G06F5/06 - G06F5/16
    • G06F2205/062—Allowing rewriting or rereading data to or from the buffer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
AU19528/83A 1982-09-23 1983-09-23 Circuit arrangement for universally usable buffer storage Abandoned AU1952883A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19823235243 DE3235243C2 (en) 1982-09-23 1982-09-23 Circuit arrangement for a universally applicable buffer memory
DE3235243 1982-09-23

Publications (1)

Publication Number Publication Date
AU1952883A true AU1952883A (en) 1984-03-29

Family

ID=6173966

Family Applications (1)

Application Number Title Priority Date Filing Date
AU19528/83A Abandoned AU1952883A (en) 1982-09-23 1983-09-23 Circuit arrangement for universally usable buffer storage

Country Status (2)

Country Link
AU (1) AU1952883A (en)
DE (1) DE3235243C2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0428771B1 (en) * 1989-11-21 1995-02-01 Deutsche ITT Industries GmbH Bidirectional data transfer device
SE515737C2 (en) * 1995-03-22 2001-10-01 Ericsson Telefon Ab L M Apparatus and method for handling digital signals and a processing device comprising such
DE19722433A1 (en) 1997-05-28 1998-12-03 Siemens Ag Method and device for the transmission of a continuous data stream in packetized form
JP4398499B2 (en) * 2005-12-02 2010-01-13 パナソニック株式会社 Buffer control device and buffer memory device

Also Published As

Publication number Publication date
DE3235243C2 (en) 1984-07-19
DE3235243A1 (en) 1984-03-29

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