AU1375101A - Modified move to rear list system and methods for thread scheduling - Google Patents

Modified move to rear list system and methods for thread scheduling

Info

Publication number
AU1375101A
AU1375101A AU13751/01A AU1375101A AU1375101A AU 1375101 A AU1375101 A AU 1375101A AU 13751/01 A AU13751/01 A AU 13751/01A AU 1375101 A AU1375101 A AU 1375101A AU 1375101 A AU1375101 A AU 1375101A
Authority
AU
Australia
Prior art keywords
methods
thread scheduling
list system
rear list
modified move
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU13751/01A
Inventor
Eric G. Manning
James C. Pang
Gholamali C. Shoja
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victoria University of Innovation and Development Corp
Original Assignee
Victoria University of Innovation and Development Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US43699599A priority Critical
Priority to US09436995 priority
Application filed by Victoria University of Innovation and Development Corp filed Critical Victoria University of Innovation and Development Corp
Priority to PCT/CA2000/001339 priority patent/WO2001035209A2/en
Publication of AU1375101A publication Critical patent/AU1375101A/en
Application status is Abandoned legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4843Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
AU13751/01A 1999-11-09 2000-11-09 Modified move to rear list system and methods for thread scheduling Abandoned AU1375101A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US43699599A true 1999-11-09 1999-11-09
US09436995 1999-11-09
PCT/CA2000/001339 WO2001035209A2 (en) 1999-11-09 2000-11-09 Modified move to rear list system and methods for thread scheduling

Publications (1)

Publication Number Publication Date
AU1375101A true AU1375101A (en) 2001-06-06

Family

ID=23734635

Family Applications (1)

Application Number Title Priority Date Filing Date
AU13751/01A Abandoned AU1375101A (en) 1999-11-09 2000-11-09 Modified move to rear list system and methods for thread scheduling

Country Status (2)

Country Link
AU (1) AU1375101A (en)
WO (1) WO2001035209A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9734222B1 (en) 2004-04-06 2017-08-15 Jpmorgan Chase Bank, N.A. Methods and systems for using script files to obtain, format and transport data
US7836096B2 (en) 2006-12-14 2010-11-16 International Business Machines Corporation Method and system using date/time mutation to return data to Java applications
JP5452125B2 (en) * 2009-08-11 2014-03-26 クラリオン株式会社 Data processing apparatus and data processing method
US8811177B1 (en) 2011-11-03 2014-08-19 Jpmorgan Chase Bank, N.A. Method and system for implementing a network analysis tool for endpoints deployments

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5179702A (en) * 1989-12-29 1993-01-12 Supercomputer Systems Limited Partnership System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling
US5815689A (en) * 1997-04-04 1998-09-29 Microsoft Corporation Method and computer program product for synchronizing the processing of multiple data streams and matching disparate processing rates using a standardized clock mechanism
US5790840A (en) * 1997-08-15 1998-08-04 International Business Machines Corporation Timestamp systems, methods and computer program products for data processing system

Also Published As

Publication number Publication date
WO2001035209A2 (en) 2001-05-17
WO2001035209A3 (en) 2001-12-06

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase
TH Corrigenda

Free format text: IN VOL 15, NO 35, PAGE(S) 7527-7530 UNDER THE HEADING APPLICATIONS LAPSED, REFUSED OR WITHDRAWN PLEASE DELETE ALL REFERENCE TO APPLICATION NOS. 11621/01, 14222/01, 17396/01, 13751/01 AND 13144/01

MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase