AU1078099A - Method and apparatus for optimizing instruction execution - Google Patents

Method and apparatus for optimizing instruction execution

Info

Publication number
AU1078099A
AU1078099A AU10780/99A AU1078099A AU1078099A AU 1078099 A AU1078099 A AU 1078099A AU 10780/99 A AU10780/99 A AU 10780/99A AU 1078099 A AU1078099 A AU 1078099A AU 1078099 A AU1078099 A AU 1078099A
Authority
AU
Australia
Prior art keywords
instruction execution
optimizing instruction
optimizing
execution
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU10780/99A
Other languages
English (en)
Inventor
William Y. Chen
Jack D Mills
Dale C. Morris
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute for Development of Emerging Architectures LLC
Original Assignee
Institute for Development of Emerging Architectures LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute for Development of Emerging Architectures LLC filed Critical Institute for Development of Emerging Architectures LLC
Publication of AU1078099A publication Critical patent/AU1078099A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/445—Exploiting fine grain parallelism, i.e. parallelism at instruction level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
    • G06F11/1407—Checkpointing the instruction stream
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Devices For Executing Special Programs (AREA)
AU10780/99A 1997-10-13 1998-10-09 Method and apparatus for optimizing instruction execution Abandoned AU1078099A (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US95383697A 1997-10-13 1997-10-13
US08953836 1997-10-13
US16804098A 1998-10-07 1998-10-07
US09168040 1998-10-07
PCT/US1998/021465 WO1999019795A1 (en) 1997-10-13 1998-10-09 Method and apparatus for optimizing execution of load and store instructions

Publications (1)

Publication Number Publication Date
AU1078099A true AU1078099A (en) 1999-05-03

Family

ID=26863747

Family Applications (1)

Application Number Title Priority Date Filing Date
AU10780/99A Abandoned AU1078099A (en) 1997-10-13 1998-10-09 Method and apparatus for optimizing instruction execution

Country Status (4)

Country Link
EP (1) EP1031076A1 (ja)
JP (1) JP2001520415A (ja)
AU (1) AU1078099A (ja)
WO (1) WO1999019795A1 (ja)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1109096A3 (en) * 1999-12-17 2004-02-11 Fujitsu Limited Processor and method of controlling the same
US6598156B1 (en) * 1999-12-23 2003-07-22 Intel Corporation Mechanism for handling failing load check instructions
US7680999B1 (en) 2000-02-08 2010-03-16 Hewlett-Packard Development Company, L.P. Privilege promotion based on check of previous privilege level
US6704862B1 (en) 2000-03-06 2004-03-09 Sun Microsystems, Inc. Method and apparatus for facilitating exception handling using a conditional trap instruction
US6631460B1 (en) 2000-04-27 2003-10-07 Institute For The Development Of Emerging Architectures, L.L.C. Advanced load address table entry invalidation based on register address wraparound
JP3790683B2 (ja) 2001-07-05 2006-06-28 インターナショナル・ビジネス・マシーンズ・コーポレーション コンピュータ装置、その例外処理プログラム及びコンパイル方法
JP2008293378A (ja) 2007-05-25 2008-12-04 Panasonic Corp プログラム書き換え装置
WO2020192587A1 (zh) 2019-03-22 2020-10-01 中科寒武纪科技股份有限公司 人工智能计算装置及相关产品
CN111723921B (zh) * 2019-03-22 2024-05-14 中科寒武纪科技股份有限公司 人工智能计算装置及相关产品
US11113065B2 (en) * 2019-04-03 2021-09-07 Advanced Micro Devices, Inc. Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5692169A (en) * 1990-12-14 1997-11-25 Hewlett Packard Company Method and system for deferring exceptions generated during speculative execution
US5778219A (en) * 1990-12-14 1998-07-07 Hewlett-Packard Company Method and system for propagating exception status in data registers and for detecting exceptions from speculative operations with non-speculative operations
JP2786574B2 (ja) * 1992-05-06 1998-08-13 インターナショナル・ビジネス・マシーンズ・コーポレイション コンピュータ・システムにおける順不同ロード動作の性能を改善する方法と装置
US5799179A (en) * 1995-01-24 1998-08-25 International Business Machines Corporation Handling of exceptions in speculative instructions
US5625835A (en) * 1995-05-10 1997-04-29 International Business Machines Corporation Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor
US5903749A (en) * 1996-07-02 1999-05-11 Institute For The Development Of Emerging Architecture, L.L.C. Method and apparatus for implementing check instructions that allow for the reuse of memory conflict information if no memory conflict occurs

Also Published As

Publication number Publication date
JP2001520415A (ja) 2001-10-30
WO1999019795A8 (en) 2000-09-28
WO1999019795A1 (en) 1999-04-22
EP1031076A1 (en) 2000-08-30

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase