ATE518191T1 - Speicherabbildungssystem, anforderungssteuerung, mehrfach-verarbeitungsanordnung, zentrale interrput-request-steuerung, vorrichtung, verfahren zur steuerung des speicherzugriffs und computerprogrammprodukt - Google Patents

Speicherabbildungssystem, anforderungssteuerung, mehrfach-verarbeitungsanordnung, zentrale interrput-request-steuerung, vorrichtung, verfahren zur steuerung des speicherzugriffs und computerprogrammprodukt

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Publication number
ATE518191T1
ATE518191T1 AT07859405T AT07859405T ATE518191T1 AT E518191 T1 ATE518191 T1 AT E518191T1 AT 07859405 T AT07859405 T AT 07859405T AT 07859405 T AT07859405 T AT 07859405T AT E518191 T1 ATE518191 T1 AT E518191T1
Authority
AT
Austria
Prior art keywords
request controller
memory
mapping system
processing arrangement
interrput
Prior art date
Application number
AT07859405T
Other languages
English (en)
Inventor
Anthony Reipold
Houman Amjadi
Lukusa D Kabulepa
Andreas Kirschbaum
Adrian Traskov
Original Assignee
Continental Teves Ag & Co Ohg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Continental Teves Ag & Co Ohg filed Critical Continental Teves Ag & Co Ohg
Application granted granted Critical
Publication of ATE518191T1 publication Critical patent/ATE518191T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
AT07859405T 2007-12-17 2007-12-17 Speicherabbildungssystem, anforderungssteuerung, mehrfach-verarbeitungsanordnung, zentrale interrput-request-steuerung, vorrichtung, verfahren zur steuerung des speicherzugriffs und computerprogrammprodukt ATE518191T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2007/055170 WO2009077813A1 (en) 2007-12-17 2007-12-17 Memory mapping system, request controller, multi-processing arrangement, central interrupt request controller, apparatus, method for controlling memory access and computer program product

Publications (1)

Publication Number Publication Date
ATE518191T1 true ATE518191T1 (de) 2011-08-15

Family

ID=39747253

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07859405T ATE518191T1 (de) 2007-12-17 2007-12-17 Speicherabbildungssystem, anforderungssteuerung, mehrfach-verarbeitungsanordnung, zentrale interrput-request-steuerung, vorrichtung, verfahren zur steuerung des speicherzugriffs und computerprogrammprodukt

Country Status (5)

Country Link
US (1) US8397043B2 (de)
EP (1) EP2225645B1 (de)
CN (1) CN101903867B (de)
AT (1) ATE518191T1 (de)
WO (1) WO2009077813A1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2479915B (en) * 2010-04-29 2016-03-23 Ge Oil & Gas Uk Ltd Well production shut down
US20120110303A1 (en) * 2010-10-28 2012-05-03 International Business Machines Corporation Method for Process Synchronization of Embedded Applications in Multi-Core Systems
KR101867336B1 (ko) * 2011-07-11 2018-06-15 삼성전자주식회사 다중 프로세서를 지원하는 인터럽트 발생을 위한 장치 및 방법
US9659110B2 (en) * 2011-10-20 2017-05-23 The Boeing Company Associative memory technology for analysis of requests for proposal
JP5845902B2 (ja) * 2012-01-04 2016-01-20 トヨタ自動車株式会社 情報処理装置及びメモリアクセス管理方法
WO2014041395A1 (en) 2012-09-12 2014-03-20 Freescale Semiconductor, Inc. System-on-chip device, method of peripheral access and integrated circuit
US9904802B2 (en) 2012-11-23 2018-02-27 Nxp Usa, Inc. System on chip
US9104472B2 (en) 2013-02-04 2015-08-11 Freescale Semiconductor, Inc. Write transaction interpretation for interrupt assertion
US9781120B2 (en) 2013-07-18 2017-10-03 Nxp Usa, Inc. System on chip and method therefor
DE102014201682A1 (de) * 2014-01-30 2015-07-30 Robert Bosch Gmbh Verfahren zur Koexistenz von Software mit verschiedenen Sicherheitsstufen in einem Multicore-Prozessorsystem
US9690719B2 (en) 2014-09-11 2017-06-27 Nxp Usa, Inc. Mechanism for managing access to at least one shared integrated peripheral of a processing unit and a method of operating thereof
US9578054B1 (en) 2015-08-31 2017-02-21 Newman H-R Computer Design, LLC Hacking-resistant computer design

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5109329A (en) 1987-02-06 1992-04-28 At&T Bell Laboratories Multiprocessing method and arrangement
AU2270892A (en) 1991-06-26 1993-01-25 Ast Research, Inc. Automatic distribution of interrupts controller for a multiple processor computer system
JPH056344A (ja) * 1991-06-28 1993-01-14 Fujitsu Ltd プログラム走行情報採取処理方式
US5367689A (en) 1992-10-02 1994-11-22 Compaq Computer Corporation Apparatus for strictly ordered input/output operations for interrupt system integrity
US5778236A (en) 1996-05-17 1998-07-07 Advanced Micro Devices, Inc. Multiprocessing interrupt controller on I/O bus
US6457021B1 (en) * 1998-08-18 2002-09-24 Microsoft Corporation In-memory database system
US6845419B1 (en) 2000-01-24 2005-01-18 Freescale Semiconductor, Inc. Flexible interrupt controller that includes an interrupt force register
US7073173B1 (en) * 2000-12-04 2006-07-04 Microsoft Corporation Code and thread differential addressing via multiplex page maps
US6657632B2 (en) * 2001-01-24 2003-12-02 Hewlett-Packard Development Company, L.P. Unified memory distributed across multiple nodes in a computer graphics system
US6775730B2 (en) 2001-04-18 2004-08-10 Sony Corporation System and method for implementing a flexible interrupt mechanism
US6952749B2 (en) 2001-05-02 2005-10-04 Portalplayer, Inc. Multiprocessor interrupt handling system and method
US7650386B2 (en) * 2004-07-29 2010-01-19 Hewlett-Packard Development Company, L.P. Communication among partitioned devices
WO2008055272A2 (en) * 2006-11-04 2008-05-08 Virident Systems, Inc. Integrating data from symmetric and asymmetric memory
KR101396831B1 (ko) * 2007-03-30 2014-05-21 삼성전자주식회사 메모리 접근 제어 방법
US20080282051A1 (en) * 2007-05-08 2008-11-13 On Demand Microelectronics Methods and arrangements for controlling results of memory retrival requests

Also Published As

Publication number Publication date
EP2225645A1 (de) 2010-09-08
US20100268905A1 (en) 2010-10-21
EP2225645B1 (de) 2011-07-27
CN101903867B (zh) 2012-12-12
CN101903867A (zh) 2010-12-01
WO2009077813A1 (en) 2009-06-25
US8397043B2 (en) 2013-03-12

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