ATE507520T1 - Verfahren und vorrichtung zur erkennung von taktgattergelegenheiten bei einer elektronischen schaltung im pipeline-design - Google Patents
Verfahren und vorrichtung zur erkennung von taktgattergelegenheiten bei einer elektronischen schaltung im pipeline-designInfo
- Publication number
- ATE507520T1 ATE507520T1 AT08787252T AT08787252T ATE507520T1 AT E507520 T1 ATE507520 T1 AT E507520T1 AT 08787252 T AT08787252 T AT 08787252T AT 08787252 T AT08787252 T AT 08787252T AT E507520 T1 ATE507520 T1 AT E507520T1
- Authority
- AT
- Austria
- Prior art keywords
- electronic circuit
- pipeline
- occasions
- clock gate
- pipeline design
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/842,491 US8073669B2 (en) | 2007-08-21 | 2007-08-21 | Method and apparatus for detecting clock gating opportunities in a pipelined electronic circuit design |
| PCT/EP2008/060722 WO2009024540A2 (en) | 2007-08-21 | 2008-08-14 | Method and apparatus for detecting clock gating opportunities in a pipelined electronic circuit design |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE507520T1 true ATE507520T1 (de) | 2011-05-15 |
Family
ID=40378739
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT08787252T ATE507520T1 (de) | 2007-08-21 | 2008-08-14 | Verfahren und vorrichtung zur erkennung von taktgattergelegenheiten bei einer elektronischen schaltung im pipeline-design |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US8073669B2 (enExample) |
| EP (1) | EP2179342B1 (enExample) |
| JP (1) | JP5147944B2 (enExample) |
| KR (1) | KR20100037628A (enExample) |
| CN (1) | CN101779179B (enExample) |
| AT (1) | ATE507520T1 (enExample) |
| DE (1) | DE602008006561D1 (enExample) |
| TW (1) | TW200915724A (enExample) |
| WO (1) | WO2009024540A2 (enExample) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2456363A (en) * | 2008-01-08 | 2009-07-15 | Ibm | Methods and system for clock gating enhancement |
| US7844843B2 (en) * | 2008-12-22 | 2010-11-30 | International Business Machines Corporation | Implementing power savings in HSS clock-gating circuit |
| US8302043B2 (en) * | 2009-09-17 | 2012-10-30 | International Business Machines Corporation | Verification of logic circuit designs using dynamic clock gating |
| US9495490B2 (en) | 2012-07-16 | 2016-11-15 | International Business Machines Corporation | Active power dissipation detection based on erroneus clock gating equations |
| US10318695B2 (en) | 2013-12-05 | 2019-06-11 | International Business Machines Corporation | Phase algebra for virtual clock and mode extraction in hierarchical designs |
| US9916407B2 (en) | 2013-12-05 | 2018-03-13 | International Business Machines Corporation | Phase algebra for analysis of hierarchical designs |
| US9268889B2 (en) | 2013-12-05 | 2016-02-23 | International Business Machines Corporation | Verification of asynchronous clock domain crossings |
| US9639641B1 (en) * | 2015-08-20 | 2017-05-02 | Microsemi Storage Solutions (U.S.), Inc. | Method and system for functional verification and power analysis of clock-gated integrated circuits |
| US9928323B2 (en) | 2015-08-20 | 2018-03-27 | Microsemi Solutions (U.S.), Inc. | Method and system for functional verification and power analysis of clock-gated integrated circuits |
| KR20170025447A (ko) * | 2015-08-28 | 2017-03-08 | 삼성전자주식회사 | 클락 파워를 줄일 수 있는 집적 회로를 설계하는 방법 |
| US10684862B2 (en) | 2016-01-08 | 2020-06-16 | Mitsubishi Electric Corporation | Processor synthesis device, processor synthesis method, and computer readable medium |
| US10761559B2 (en) * | 2016-12-13 | 2020-09-01 | Qualcomm Incorporated | Clock gating enable generation |
| US10585995B2 (en) * | 2017-06-26 | 2020-03-10 | International Business Machines Corporation | Reducing clock power consumption of a computer processor |
| KR101952518B1 (ko) | 2017-09-12 | 2019-02-26 | 두산중공업 주식회사 | 파이프 지지대 설계 시스템 및 그 방법 |
| CN112100793B (zh) * | 2019-05-31 | 2023-06-13 | 超威半导体(上海)有限公司 | 用于重定时流水线的基于条带的自选通 |
| US12067335B2 (en) * | 2022-04-11 | 2024-08-20 | Arteris, Inc. | Automatic configuration of pipeline modules in an electronics system |
| US12216518B2 (en) | 2023-02-23 | 2025-02-04 | Marvell Asia Pte Ltd | Power saving in a network device |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6247134B1 (en) * | 1999-03-31 | 2001-06-12 | Synopsys, Inc. | Method and system for pipe stage gating within an operating pipelined circuit for power savings |
| US6393579B1 (en) * | 1999-12-21 | 2002-05-21 | Intel Corporation | Method and apparatus for saving power and improving performance in a collapsable pipeline using gated clocks |
| US6965991B1 (en) * | 2000-05-12 | 2005-11-15 | Pts Corporation | Methods and apparatus for power control in a scalable array of processor elements |
| US20030070013A1 (en) * | 2000-10-27 | 2003-04-10 | Daniel Hansson | Method and apparatus for reducing power consumption in a digital processor |
| US7035785B2 (en) * | 2001-12-28 | 2006-04-25 | Intel Corporation | Mechanism for estimating and controlling di/dt-induced power supply voltage variations |
| US7100060B2 (en) * | 2002-06-26 | 2006-08-29 | Intel Corporation | Techniques for utilization of asymmetric secondary processing resources |
| US7076681B2 (en) * | 2002-07-02 | 2006-07-11 | International Business Machines Corporation | Processor with demand-driven clock throttling power reduction |
| US7065665B2 (en) * | 2002-10-02 | 2006-06-20 | International Business Machines Corporation | Interlocked synchronous pipeline clock gating |
| US20040193846A1 (en) * | 2003-03-28 | 2004-09-30 | Sprangle Eric A. | Method and apparatus for utilizing multiple opportunity ports in a processor pipeline |
| US7076682B2 (en) * | 2004-05-04 | 2006-07-11 | International Business Machines Corp. | Synchronous pipeline with normally transparent pipeline stages |
| US7752426B2 (en) * | 2004-08-30 | 2010-07-06 | Texas Instruments Incorporated | Processes, circuits, devices, and systems for branch prediction and other processor improvements |
| US7653807B2 (en) * | 2005-09-19 | 2010-01-26 | Synopsys, Inc. | Removing a pipeline bubble by blocking clock signal to downstream stage when downstream stage contains invalid data |
| US7401242B2 (en) * | 2005-09-27 | 2008-07-15 | International Business Machines Corporation | Dynamic power management in a processor design |
| US7797561B1 (en) * | 2006-12-21 | 2010-09-14 | Nvidia Corporation | Automatic functional block level clock-gating |
| US7802118B1 (en) * | 2006-12-21 | 2010-09-21 | Nvidia Corporation | Functional block level clock-gating within a graphics processor |
| US7958483B1 (en) * | 2006-12-21 | 2011-06-07 | Nvidia Corporation | Clock throttling based on activity-level signals |
| JP4388965B2 (ja) * | 2007-02-13 | 2009-12-24 | 富士通株式会社 | クロックゲーティング解析プログラム、該プログラムを記録した記録媒体、クロックゲーティング解析装置、およびクロックゲーティング解析方法 |
| US20080307240A1 (en) * | 2007-06-08 | 2008-12-11 | Texas Instruments Incorporated | Power management electronic circuits, systems, and methods and processes of manufacture |
-
2007
- 2007-08-21 US US11/842,491 patent/US8073669B2/en active Active
-
2008
- 2008-08-14 DE DE602008006561T patent/DE602008006561D1/de active Active
- 2008-08-14 AT AT08787252T patent/ATE507520T1/de not_active IP Right Cessation
- 2008-08-14 KR KR1020107003180A patent/KR20100037628A/ko not_active Abandoned
- 2008-08-14 JP JP2010521403A patent/JP5147944B2/ja active Active
- 2008-08-14 WO PCT/EP2008/060722 patent/WO2009024540A2/en not_active Ceased
- 2008-08-14 EP EP08787252A patent/EP2179342B1/en active Active
- 2008-08-14 CN CN2008801024824A patent/CN101779179B/zh active Active
- 2008-08-18 TW TW097131470A patent/TW200915724A/zh unknown
Also Published As
| Publication number | Publication date |
|---|---|
| TW200915724A (en) | 2009-04-01 |
| JP2010537293A (ja) | 2010-12-02 |
| US8073669B2 (en) | 2011-12-06 |
| US20090055668A1 (en) | 2009-02-26 |
| EP2179342B1 (en) | 2011-04-27 |
| JP5147944B2 (ja) | 2013-02-20 |
| KR20100037628A (ko) | 2010-04-09 |
| CN101779179A (zh) | 2010-07-14 |
| CN101779179B (zh) | 2012-07-11 |
| WO2009024540A2 (en) | 2009-02-26 |
| DE602008006561D1 (de) | 2011-06-09 |
| WO2009024540A3 (en) | 2009-09-17 |
| EP2179342A2 (en) | 2010-04-28 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |