ATE504039T1 - Hardwaregetriggerte daten-cacheleitungs- vorzuteilung - Google Patents

Hardwaregetriggerte daten-cacheleitungs- vorzuteilung

Info

Publication number
ATE504039T1
ATE504039T1 AT08702517T AT08702517T ATE504039T1 AT E504039 T1 ATE504039 T1 AT E504039T1 AT 08702517 T AT08702517 T AT 08702517T AT 08702517 T AT08702517 T AT 08702517T AT E504039 T1 ATE504039 T1 AT E504039T1
Authority
AT
Austria
Prior art keywords
allocation
cache line
cache
store operation
programmable
Prior art date
Application number
AT08702517T
Other languages
English (en)
Inventor
De Waerdt Jan-Willem Van
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE504039T1 publication Critical patent/ATE504039T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0855—Overlapped cache accessing, e.g. pipeline
    • G06F12/0859—Overlapped cache accessing, e.g. pipeline with reload from main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6028—Prefetching based on hints or prefetch instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Circuits Of Receivers In General (AREA)
  • Information Transfer Systems (AREA)
AT08702517T 2007-01-25 2008-01-24 Hardwaregetriggerte daten-cacheleitungs- vorzuteilung ATE504039T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US88659807P 2007-01-25 2007-01-25
PCT/IB2008/050262 WO2008090525A2 (en) 2007-01-25 2008-01-24 Hardware triggered data cache line pre-allocation

Publications (1)

Publication Number Publication Date
ATE504039T1 true ATE504039T1 (de) 2011-04-15

Family

ID=39493904

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08702517T ATE504039T1 (de) 2007-01-25 2008-01-24 Hardwaregetriggerte daten-cacheleitungs- vorzuteilung

Country Status (6)

Country Link
US (1) US20100077151A1 (de)
EP (1) EP2115598B1 (de)
CN (1) CN101589373A (de)
AT (1) ATE504039T1 (de)
DE (1) DE602008005851D1 (de)
WO (1) WO2008090525A2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120324195A1 (en) * 2011-06-14 2012-12-20 Alexander Rabinovitch Allocation of preset cache lines
US8429315B1 (en) 2011-06-24 2013-04-23 Applied Micro Circuits Corporation Stashing system and method for the prevention of cache thrashing
US9336162B1 (en) 2012-02-16 2016-05-10 Applied Micro Circuits Corporation System and method for pre-fetching data based on a FIFO queue of packet messages reaching a first capacity threshold
WO2015057857A1 (en) * 2013-10-15 2015-04-23 Mill Computing, Inc. Computer processor employing dedicated hardware mechanism controlling the initialization and invalidation of cache lines
US20150134933A1 (en) * 2013-11-14 2015-05-14 Arm Limited Adaptive prefetching in a data processing apparatus
WO2019029793A1 (en) * 2017-08-08 2019-02-14 Continental Automotive Gmbh METHOD FOR OPERATING A CACHE MEMORY
CN110058964B (zh) * 2018-01-18 2023-05-02 伊姆西Ip控股有限责任公司 数据恢复方法、数据恢复系统和计算机可读介质

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5903911A (en) * 1993-06-22 1999-05-11 Dell Usa, L.P. Cache-based computer system employing memory control circuit and method for write allocation and data prefetch
US5642494A (en) * 1994-12-21 1997-06-24 Intel Corporation Cache memory with reduced request-blocking
US5829025A (en) * 1996-12-17 1998-10-27 Intel Corporation Computer system and method of allocating cache memories in a multilevel cache hierarchy utilizing a locality hint within an instruction
US5822790A (en) * 1997-02-07 1998-10-13 Sun Microsystems, Inc. Voting data prefetch engine
US6393528B1 (en) * 1999-06-30 2002-05-21 International Business Machines Corporation Optimized cache allocation algorithm for multiple speculative requests
US6594730B1 (en) * 1999-08-03 2003-07-15 Intel Corporation Prefetch system for memory controller
US7234040B2 (en) * 2002-01-24 2007-06-19 University Of Washington Program-directed cache prefetching for media processors
US6760818B2 (en) * 2002-05-01 2004-07-06 Koninklijke Philips Electronics N.V. Memory region based data pre-fetching
US7197605B2 (en) * 2002-12-30 2007-03-27 Intel Corporation Allocating cache lines
WO2005091146A1 (ja) * 2004-03-24 2005-09-29 Matsushita Electric Industrial Co., Ltd. キャッシュメモリ及びその制御方法
US7350029B2 (en) * 2005-02-10 2008-03-25 International Business Machines Corporation Data stream prefetching in a microprocessor
US8490065B2 (en) * 2005-10-13 2013-07-16 International Business Machines Corporation Method and apparatus for software-assisted data cache and prefetch control
US8225046B2 (en) * 2006-09-29 2012-07-17 Intel Corporation Method and apparatus for saving power by efficiently disabling ways for a set-associative cache
US7600077B2 (en) * 2007-01-10 2009-10-06 Arm Limited Cache circuitry, data processing apparatus and method for handling write access requests

Also Published As

Publication number Publication date
EP2115598B1 (de) 2011-03-30
DE602008005851D1 (de) 2011-05-12
US20100077151A1 (en) 2010-03-25
WO2008090525A2 (en) 2008-07-31
EP2115598A2 (de) 2009-11-11
WO2008090525A3 (en) 2008-09-18
CN101589373A (zh) 2009-11-25

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